Contrasting a NoC and a traditional interconnect fabric with layout awareness

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Angiolini, Federico ^a   Meloni, Paolo ^b   Carta, Salvatore ^b   Benini, Luca ^a   Raffo, Luigi ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b UNIVERSITY OF CAGLIARI   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; PACKET NETWORKS; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING; SCALABILITY; SYSTEMS ANALYSIS;

CONTRASTIVE ANALYSIS; ELECTRONIC DESIGNERS; INTERCONNECT SYSTEMS;

MULTIPROCESSING SYSTEMS;

EID: 34047170421     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244033     Document Type: Conference Paper

References (23)

1. A. Andriahantenaina and A. Greiner. Micro-network for SoC: Implementation of a 32-port SPIN network. In The Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pages 1128-1129. IEEE, 2003.
2. F. Angiolini, P. Meloni, D. Bertozzi, L. Benini, S. Carta, and L. Raffo. Networks on chips: A synthesis perspective. In Proceedings of the 2005 ParCo Conference (to be published), 2005.
3. ARM Ltd. The Advanced Microcontroller Bus Architecture (AMBA) homepage. www.arm.com/products/solutions/AMBAHomePage.html.
4. L. Benini and G. D. Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70 - 78, January 2002.
5. D. Bertozzi, A. Jalabert, S. Murali, R. R. Tamhankar, S. Stergiou, L. Benini, and G. D. Micheli. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Transactions on Parallel and Distributed Systems, 16, Issue 2:113-129, February 2005.
6. T. Bjerregaard and J. Sparsø. Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip. In Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 34-43, 2005.
7. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny. QNoC: QoS architecture and design process for network on chip. In Journal of Systems Architecture. Elsevier, 2004.
8. Cadence Design Systems Inc. SoC Encounter. www.cadence.com.
9. W. J. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th Design Automation Conference, pages 684-689, June 2001.
10. F. Karim, A. Nguyen, S. Dey, and R. Rao. On-chip communication architecture for OC-768 network processors. In Proceedings of the Design Automation Conference (DAC), pages 678-683, 2001.
11. K. Lee, S.-J. Lee, S.-E. Kim, H.-M. Choi, D. Kim, S. Kim, M.-W. Lee, and H.-J. Yoo. A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform. In Digest of Technical Papers of the 2004 IEEE International Solid-State Circuits Conference (ISSC), pages 152-518. IEEE Computer Society, 2004.
12. Open Core Protocol Specification, Release 2.0. www.ocpip.org, 2003.
13. A. Pullini, F. Angiolini, D. Bertozzi, and L. Benini. Fault tolerance overhead in network-on-chip flow control schemes. In Proceedings of the SBCCI Conference 2005 (to be published), 2005.
14. E. Rijpkema, K. G. W. Goossens, A. Radulescu, J. Dielissen, J. V. Meerbergen, P. Wielage, and E. Waterlander. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. In Proceedings of the Design, Automation and Test in Europe Conference, pages 350-355. IEEE, 2003.
15. S. Stergiou, F. Angiolini, S. Carta, L. Raffo, D. Bertozzi, and G. D. Micheli. xpipes Lite: A synthesis oriented design library for networks on chips. In Proceedings of the 2005 Design, Automation and Test in Europe Conference (DATE'05), pages 1188-1193. IEEE, 2005.
16. STMicroelectronics. The STBus interconnect. www.st.com.
17. Synopsys Inc. coreTools. www.synopsys.org.
18. Synopsys Inc. Design Compiler, www.synopsys.org.
19. Synopsys Inc. PrimePower. www.synopsys.org.
20. D. Wiklund and D. Liu. SoCBUS: Switched network on chip for hard real time embedded systems. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS03). IEEE, 2003.
21. D. Wingard. Micronetwork-based integration for socs. In Proceedings of the 38th Design Automation Conference (DAC), pages 673-677. ACM, June 2001.
22. J. Xu, W. Wolf, J. Henkel, and S. Chakradhar. A methodology for design, modeling, and analysis of networks-on-chip. In Proceedings of the 2005 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1778-1781. IEEE Computer Society, 2005.
23. C. A. Zeferino and A. A. Susin. SoCIN: A parametric and scalable network-on-chip. In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCC103), pages 34-43, 2003.