-
1
-
-
12944288247
-
Vector unit architecture for emotion synthesis
-
Kunimatsu A., Ide N., Sato T., Endo Y., Murakami H., Kamei T., Hirano M., Ishihara F., Tago H., Oka M., Ohba A., Yutaka T., Okada T., Suzuoki M. Vector unit architecture for emotion synthesis. IEEE Micro 2000, 20(2):40-47.
-
(2000)
IEEE Micro
, vol.20
, Issue.2
, pp. 40-47
-
-
Kunimatsu, A.1
Ide, N.2
Sato, T.3
Endo, Y.4
Murakami, H.5
Kamei, T.6
Hirano, M.7
Ishihara, F.8
Tago, H.9
Oka, M.10
Ohba, A.11
Yutaka, T.12
Okada, T.13
Suzuoki, M.14
-
3
-
-
0031236158
-
Baring it all to software: raw machines
-
Waingold E., Taylor M., Srikrishna D., Sarkar V., Lee W., Lee V., Kim J., Frank M., Finch P., Barua R., Babb J., Amarasinghe S., Agarwal A. Baring it all to software: raw machines. IEEE Computer 1997, 30(9):86-93.
-
(1997)
IEEE Computer
, vol.30
, Issue.9
, pp. 86-93
-
-
Waingold, E.1
Taylor, M.2
Srikrishna, D.3
Sarkar, V.4
Lee, W.5
Lee, V.6
Kim, J.7
Frank, M.8
Finch, P.9
Barua, R.10
Babb, J.11
Amarasinghe, S.12
Agarwal, A.13
-
5
-
-
0034428118
-
Systemlevel design: orthogonalization of concerns and platform-based design
-
Keutzer K., Newton A.R., Rabaey J.M., Sangiovanni-Vincentelli A. Systemlevel design: orthogonalization of concerns and platform-based design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2000, 19(12).
-
(2000)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.19
, Issue.12
-
-
Keutzer, K.1
Newton, A.R.2
Rabaey, J.M.3
Sangiovanni-Vincentelli, A.4
-
6
-
-
0032638580
-
How VSIA answers the SOC dilemma
-
Birnbaum M., Sachs H. How VSIA answers the SOC dilemma. IEEE Computer 1999, 32(6):42-50.
-
(1999)
IEEE Computer
, vol.32
, Issue.6
, pp. 42-50
-
-
Birnbaum, M.1
Sachs, H.2
-
7
-
-
0035444259
-
Viper: a multiprocessor SOC for advanced set-top box and digital TV systems
-
September/October
-
Dutta S., et al. Viper: a multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design & Test of Computers September/October 2001.
-
(2001)
IEEE Design & Test of Computers
-
-
Dutta, S.1
-
8
-
-
0033892359
-
EPIC: explicitly parallel instruction computing
-
Schlansker M.S., Rau B.R. EPIC: explicitly parallel instruction computing. IEEE Computer 2000, 33(2):37-45.
-
(2000)
IEEE Computer
, vol.33
, Issue.2
, pp. 37-45
-
-
Schlansker, M.S.1
Rau, B.R.2
-
9
-
-
0036916198
-
Optimization and control of vDD and vT for low power, high speed CMOS design
-
November
-
Kuroda T. Optimization and control of vDD and vT for low power, high speed CMOS design. International Conference on Computer Aided Design November, 2002, 28-34.
-
(2002)
International Conference on Computer Aided Design
, pp. 28-34
-
-
Kuroda, T.1
-
11
-
-
0036916414
-
Methods for true power minimization
-
November
-
Brodersen R., Horowitz M., Markovic D., Nikolic B., Stojanovic V. Methods for true power minimization. International Conference on Computer Aided Design November, 2002, 35-42.
-
(2002)
International Conference on Computer Aided Design
, pp. 35-42
-
-
Brodersen, R.1
Horowitz, M.2
Markovic, D.3
Nikolic, B.4
Stojanovic, V.5
-
12
-
-
0003850954
-
-
Prentice Hall, Englewood Cliffs, NJ
-
Rabaey J., Chandrakasan A., Nikolic B. Digital Integrated Circuits: A Design Perspective 2003, Prentice Hall, Englewood Cliffs, NJ.
-
(2003)
Digital Integrated Circuits: A Design Perspective
-
-
Rabaey, J.1
Chandrakasan, A.2
Nikolic, B.3
-
14
-
-
49749146140
-
-
November, ICCAD
-
Martin S., Flautner K., Mudge T., Blaauw V. Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads November, 2002, 712-725. ICCAD.
-
(2002)
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads
, pp. 712-725
-
-
Martin, S.1
Flautner, K.2
Mudge, T.3
Blaauw, V.4
-
16
-
-
0034875609
-
Power-aware partitioned cache architectures
-
Kim S., Vijaykrishnan N., Kandemir M., Sivasubramaniam A., Irwin M.J., Geethanjali E. Power-aware partitioned cache architectures. Proceedings of the 2001 International Symposium on Low Power Electronics and Design (ISLPED'01) 2001, 64-67.
-
(2001)
Proceedings of the 2001 International Symposium on Low Power Electronics and Design (ISLPED'01)
, pp. 64-67
-
-
Kim, S.1
Vijaykrishnan, N.2
Kandemir, M.3
Sivasubramaniam, A.4
Irwin, M.J.5
Geethanjali, E.6
-
19
-
-
0035693947
-
Reducing set-associative cache energy via way-prediction and selective direct-mapping
-
Powell M.D., Agarwal A., Vijaykumar T.N., Falsafi B., Roy K. Reducing set-associative cache energy via way-prediction and selective direct-mapping. Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture 2001, 54-65.
-
(2001)
Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture
, pp. 54-65
-
-
Powell, M.D.1
Agarwal, A.2
Vijaykumar, T.N.3
Falsafi, B.4
Roy, K.5
-
24
-
-
0034825598
-
An integrated circuit/architecture approach to reducing leakage in deep-submicron high- performance I-caches
-
Yang S., Powell M.D., Falsafi B., Roy K., Vijaykumar T.N. An integrated circuit/architecture approach to reducing leakage in deep-submicron high- performance I-caches. Proceedings of Seventh International Symposium on High-Performance Computer Architecture (HPCA-7) 2001, 147-157.
-
(2001)
Proceedings of Seventh International Symposium on High-Performance Computer Architecture (HPCA-7)
, pp. 147-157
-
-
Yang, S.1
Powell, M.D.2
Falsafi, B.3
Roy, K.4
Vijaykumar, T.N.5
-
26
-
-
33750705950
-
Tuning garbage collection in an embedded java environment
-
Chen G., Shetty R., Kandemir M., Vijaykrishnan N., Irwin M.J., Wolczko M. Tuning garbage collection in an embedded java environment. Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA-8) 2002, 80-91.
-
(2002)
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA-8)
, pp. 80-91
-
-
Chen, G.1
Shetty, R.2
Kandemir, M.3
Vijaykrishnan, N.4
Irwin, M.J.5
Wolczko, M.6
-
27
-
-
1142282798
-
Standby-current reduction for deep sub-micron VLSI CMOS circuits: smart series switch
-
December
-
der Meer P.R.V., Staveren A.V. Standby-current reduction for deep sub-micron VLSI CMOS circuits: smart series switch. The ProRISC/IEEE Workshop December, 2000, 401-404.
-
(2000)
The ProRISC/IEEE Workshop
, pp. 401-404
-
-
der Meer, P.R.V.1
Staveren, A.V.2
-
30
-
-
0035177403
-
Adaptive mode control: a static-power-efficient cache design
-
September
-
Zhou H., Toburen M.C., Rotenberg E., Conte T.M. Adaptive mode control: a static-power-efficient cache design. The 10th International Conference on Parallel Architectures and Compilation Techniques (PACT'01) September, 2001, 61-70.
-
(2001)
The 10th International Conference on Parallel Architectures and Compilation Techniques (PACT'01)
, pp. 61-70
-
-
Zhou, H.1
Toburen, M.C.2
Rotenberg, E.3
Conte, T.M.4
-
31
-
-
0036294454
-
Drowsy caches: simple techniques for reducing leakage power
-
Flautner K., Kim N.S., Martin S., Blaauw D., Mudge T. Drowsy caches: simple techniques for reducing leakage power. Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA-29) 2002, 148-157.
-
(2002)
Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA-29)
, pp. 148-157
-
-
Flautner, K.1
Kim, N.S.2
Martin, S.3
Blaauw, D.4
Mudge, T.5
-
35
-
-
0035506737
-
A 250-MHz single-chip multiprocessor for audio and video signal processing
-
Koyama T., Inoue K., Hanaki H., Yasue M., Iwata E. A 250-MHz single-chip multiprocessor for audio and video signal processing. IEEE Journal of Solid-State Circuits 2001, 36(11):1768-1774.
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, Issue.11
, pp. 1768-1774
-
-
Koyama, T.1
Inoue, K.2
Hanaki, H.3
Yasue, M.4
Iwata, E.5
-
36
-
-
0030259458
-
The case for a single-chip multiprocessor
-
Olukotun K., Nayfeh B.A., Hammond L., Wilson K., Chang K. The case for a single-chip multiprocessor. The 8th Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IIV) 1996, 2-11.
-
(1996)
The 8th Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IIV)
, pp. 2-11
-
-
Olukotun, K.1
Nayfeh, B.A.2
Hammond, L.3
Wilson, K.4
Chang, K.5
-
37
-
-
0029700352
-
A shared-bus control mechanism and a cache coherence protocol for a high-performance on-chip multiprocessor
-
February
-
Takahashi M., Takano H., Kaneko E., Suzuki S. A shared-bus control mechanism and a cache coherence protocol for a high-performance on-chip multiprocessor. 2nd IEEE Symposium on High-Performance Computer Architecture (HPCA'96) February, 1996, 314-322.
-
(1996)
2nd IEEE Symposium on High-Performance Computer Architecture (HPCA'96)
, pp. 314-322
-
-
Takahashi, M.1
Takano, H.2
Kaneko, E.3
Suzuki, S.4
-
38
-
-
0029179077
-
The splash-2 programs: characterization and methodological considerations
-
Woo S.C., Ohara M., Torrie E., Singh J., Gupta A. The splash-2 programs: characterization and methodological considerations. Proceedings of the 22nd Annual International Symposium on Computer Architecture 1995, 24-36.
-
(1995)
Proceedings of the 22nd Annual International Symposium on Computer Architecture
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.4
Gupta, A.5
-
39
-
-
0034825054
-
JETTY: filtering snoops for reduced energy consumption in SMP servers
-
January
-
Moshovos A., et al. JETTY: filtering snoops for reduced energy consumption in SMP servers. Proceedings of HPCA January, 2001, 85-96.
-
(2001)
Proceedings of HPCA
, pp. 85-96
-
-
Moshovos, A.1
-
41
-
-
33646391831
-
Evaluation of snoop-energy reduction techniques for chip-multiprocessors
-
in conjunction with ISCA
-
Ekman M., Dahlgren F., Stenstrm P. Evaluation of snoop-energy reduction techniques for chip-multiprocessors. Proceedings of the Workshop on Duplicating, Deconstructing, and Debunking 2002, in conjunction with ISCA.
-
(2002)
Proceedings of the Workshop on Duplicating, Deconstructing, and Debunking
-
-
Ekman, M.1
Dahlgren, F.2
Stenstrm, P.3
-
43
-
-
0036630112
-
Bus encoding architecture for low-power implementation of an AMBA-based SoC Platform
-
4
-
Osborne S., Erdogan A., Arslan T., Robinson D. Bus encoding architecture for low-power implementation of an AMBA-based SoC Platform. IEEE Proceedings: Computers and Digital Techniques 2002, 149:152-156. 4.
-
(2002)
IEEE Proceedings: Computers and Digital Techniques
, vol.149
, pp. 152-156
-
-
Osborne, S.1
Erdogan, A.2
Arslan, T.3
Robinson, D.4
-
46
-
-
0031342532
-
Low-power encodings for global communication in CMOS VLSI
-
Stan M., Burleson W. Low-power encodings for global communication in CMOS VLSI. IEEE Transactions on VLSI Systems 1997, 5(4):444-455.
-
(1997)
IEEE Transactions on VLSI Systems
, vol.5
, Issue.4
, pp. 444-455
-
-
Stan, M.1
Burleson, W.2
-
49
-
-
0032287846
-
Working-zone encoding for reducing the energy in microprocessor address buses
-
Musoll E., Lang T., Cortadella J. Working-zone encoding for reducing the energy in microprocessor address buses. IEEE Transactions on VLSI Systems 1998, 6(4):568-572.
-
(1998)
IEEE Transactions on VLSI Systems
, vol.6
, Issue.4
, pp. 568-572
-
-
Musoll, E.1
Lang, T.2
Cortadella, J.3
-
51
-
-
0030644909
-
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
-
March
-
Benini L., De Micheli G., Macii E., Sciuto D., Silvano C. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems. Great Lakes Symposium on VLSI March, 1997, 77-82.
-
(1997)
Great Lakes Symposium on VLSI
, pp. 77-82
-
-
Benini, L.1
De Micheli, G.2
Macii, E.3
Sciuto, D.4
Silvano, C.5
-
54
-
-
0032300757
-
Reducing power consumption of core-based systems by address bus encoding
-
Benini L., De Micheli G., Macii E., Poncino M., Quer S. Reducing power consumption of core-based systems by address bus encoding. IEEE Transactions on VLSI Systems 1998, 6(4):554-562.
-
(1998)
IEEE Transactions on VLSI Systems
, vol.6
, Issue.4
, pp. 554-562
-
-
Benini, L.1
De Micheli, G.2
Macii, E.3
Poncino, M.4
Quer, S.5
-
55
-
-
0032660358
-
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
-
June
-
Benini L., Macii A., Macii E., Poncino M., Scarsi R. Synthesis of low-overhead interfaces for power-efficient communication over wide buses. Design Automation Conference June, 1999, 128-133.
-
(1999)
Design Automation Conference
, pp. 128-133
-
-
Benini, L.1
Macii, A.2
Macii, E.3
Poncino, M.4
Scarsi, R.5
-
57
-
-
0034483997
-
Coupling-driven signal encoding scheme for low-power interface design
-
Kim K-W., Baek K.-H., Shanbhag N., Liu C-L., Kang S-M. Coupling-driven signal encoding scheme for low-power interface design. International Conference on Computer Aided Design 2000, 318-321.
-
(2000)
International Conference on Computer Aided Design
, pp. 318-321
-
-
Kim, K.-W.1
Baek, K.-H.2
Shanbhag, N.3
Liu, C.-L.4
Kang, S.-M.5
-
59
-
-
0033704034
-
Low-swing on-chip signaling techniques: effectiveness and robustness
-
Hui Z., George V., Rabaey J. Low-swing on-chip signaling techniques: effectiveness and robustness. IEEE Transactions on VLSI Systems 2000, 8(3):264-272.
-
(2000)
IEEE Transactions on VLSI Systems
, vol.8
, Issue.3
, pp. 264-272
-
-
Hui, Z.1
George, V.2
Rabaey, J.3
-
60
-
-
0035392122
-
Optimum voltage swing on on-chip and off-chip interconnect
-
Svensson C. Optimum voltage swing on on-chip and off-chip interconnect. IEEE Journal of Solid-State Circuits 2001, 36(7):1108-1112.
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, Issue.7
, pp. 1108-1112
-
-
Svensson, C.1
-
63
-
-
0036149420
-
Networks on chips: a new SoC paradigm
-
Benini L., De Micheli G. Networks on chips: a new SoC paradigm. IEEE Computer 2002, 35:70-78.
-
(2002)
IEEE Computer
, vol.35
, pp. 70-78
-
-
Benini, L.1
De Micheli, G.2
-
66
-
-
0034848112
-
Route packets, not wires: on-chip interconnection networks
-
Dally W.J., Towles B. Route packets, not wires: on-chip interconnection networks. DAC 2001 June, 2001, 684-689.
-
(2001)
DAC 2001
, pp. 684-689
-
-
Dally, W.J.1
Towles, B.2
-
70
-
-
0004214375
-
Adaptive Parallelism with Piranha
-
Yale University, New Haven, CT
-
Carriero N., Gelernter D., Kaminsky D., Westbrook J. Adaptive Parallelism with Piranha. Technical Report 954 1993, Yale University, New Haven, CT.
-
(1993)
Technical Report 954
-
-
Carriero, N.1
Gelernter, D.2
Kaminsky, D.3
Westbrook, J.4
-
74
-
-
0031673406
-
Reducing power consumption of dedicated processors through instruction set encoding
-
February
-
Benini L., De Micheli G., Macii A., Macii E., Poncino M. Reducing power consumption of dedicated processors through instruction set encoding. Great Lakes Symposium on VLSI February, 1998, 8-12.
-
(1998)
Great Lakes Symposium on VLSI
, pp. 8-12
-
-
Benini, L.1
De Micheli, G.2
Macii, A.3
Macii, E.4
Poncino, M.5
-
75
-
-
84893775814
-
-
Design Automation and Test in Europe, February
-
Benini, L., De Micheli, G., Macii, E., Sciuto, D., and Silvano, C. Address bus encoding techniques for system-level power optimization, in Design Automation and Test in Europe, pp. 861-866, February, 1998.
-
(1998)
Address bus encoding techniques for system-level power optimization
, pp. 861-866
-
-
Benini, L.1
De Micheli, G.2
Macii, E.3
Sciuto, D.4
Silvano, C.5
-
76
-
-
0033097604
-
Segmented bus design for low-power systems
-
Chen J., Jone W., Wang J., Lu H., Chen T. Segmented bus design for low-power systems. IEEE Transactions on VLSI Systems 1999, 7(1):25-29.
-
(1999)
IEEE Transactions on VLSI Systems
, vol.7
, Issue.1
, pp. 25-29
-
-
Chen, J.1
Jone, W.2
Wang, J.3
Lu, H.4
Chen, T.5
-
77
-
-
0033341913
-
Low power chip interface based on bus data encoding with adaptive code-book method
-
Komatsh S., Ikeda M., Asada K. Low power chip interface based on bus data encoding with adaptive code-book method. Great Lakes Symposium on VLSI 1999, 368-371.
-
(1999)
Great Lakes Symposium on VLSI
, pp. 368-371
-
-
Komatsh, S.1
Ikeda, M.2
Asada, K.3
-
80
-
-
84891377982
-
EAC: a compiler framework for high-level energy estimation and optimization
-
March
-
Kadayif I., Kandemir M., Vijaykrishnan N., Irwin M.J., Sivasubramaniam A. EAC: a compiler framework for high-level energy estimation and optimization. Proceedings of the 5th Design Automation and Test in Europe Conference (DATE'02) March, 2002.
-
(2002)
Proceedings of the 5th Design Automation and Test in Europe Conference (DATE'02)
-
-
Kadayif, I.1
Kandemir, M.2
Vijaykrishnan, N.3
Irwin, M.J.4
Sivasubramaniam, A.5
-
86
-
-
0033903824
-
A Global Wiring Paradigm for Deep Submicron Design
-
February
-
Sylvester D., Keutzer K. A Global Wiring Paradigm for Deep Submicron Design. IEEE Transactions on CAD/ICAS February 2000, Vol. 19(No. 2):242-252.
-
(2000)
IEEE Transactions on CAD/ICAS
, vol.19
, Issue.2
, pp. 242-252
-
-
Sylvester, D.1
Keutzer, K.2
-
87
-
-
0033689943
-
The future of Interconnection Technology
-
May
-
Theis T. The future of Interconnection Technology. IBM Journal of Research and Development May 2000, Vol. 44(No. 3):379-390.
-
(2000)
IBM Journal of Research and Development
, vol.44
, Issue.3
, pp. 379-390
-
-
Theis, T.1
-
88
-
-
0031999149
-
Electrical Characteristics of Interconnections for High-Performance Systems
-
February no. 2
-
Deutsch A. Electrical Characteristics of Interconnections for High-Performance Systems. Proceedings of the IEEE February 1998, vol. 86:315-355. no. 2.
-
(1998)
Proceedings of the IEEE
, vol.86
, pp. 315-355
-
-
Deutsch, A.1
-
91
-
-
0034428335
-
DSCDMA Wired Bus with Simple Interconnection Topology for Parallel Processing System LSIs
-
Jan
-
Yoshimura R., Koat T., Hatanaka S., Matsuoka T., Taniguchi K. DSCDMA Wired Bus with Simple Interconnection Topology for Parallel Processing System LSIs. IEEE Solid-State Circuits Conference Jan. 2000, 371.
-
(2000)
IEEE Solid-State Circuits Conference
, pp. 371
-
-
Yoshimura, R.1
Koat, T.2
Hatanaka, S.3
Matsuoka, T.4
Taniguchi, K.5
-
94
-
-
0033314263
-
Soft Error Considerations for Deep Submicron CMOS Circuit Applications, IEDM
-
Cohen N., Sriram T., Leland N., Moyer D., Butler R., Flatley S. Soft Error Considerations for Deep Submicron CMOS Circuit Applications, IEDM. Proceedings of IEEE International Electron Device Meeting 1999, 315-318.
-
(1999)
Proceedings of IEEE International Electron Device Meeting
, pp. 315-318
-
-
Cohen, N.1
Sriram, T.2
Leland, N.3
Moyer, D.4
Butler, R.5
Flatley, S.6
-
95
-
-
0003018713
-
Time Redundancy Based Soft Error Tolerance to Rescue Nanometer Technologies
-
Nicolaidis M. Time Redundancy Based Soft Error Tolerance to Rescue Nanometer Technologies. Proceedings VTS 1999.
-
(1999)
Proceedings VTS
-
-
Nicolaidis, M.1
-
96
-
-
0032300757
-
Power Optimization of Corebased Systems by Address Bus Encoding
-
Dec
-
Benini L., De Micheli G., Macii E., Poncino M., Quer S. Power Optimization of Corebased Systems by Address Bus Encoding. IEEE Transactions on Very Large Scale Integration Systems Dec. 1998, vol. 6(no. 4):5785-5788.
-
(1998)
IEEE Transactions on Very Large Scale Integration Systems
, vol.6
, Issue.4
, pp. 5785-5788
-
-
Benini, L.1
De Micheli, G.2
Macii, E.3
Poncino, M.4
Quer, S.5
-
99
-
-
0032597714
-
An Efficient Bus Architecture for System-on-chip Design
-
Cordan B. An Efficient Bus Architecture for System-on-chip Design. IEEE Custom Integrated Circuits Conference 1999, 623-626.
-
(1999)
IEEE Custom Integrated Circuits Conference
, pp. 623-626
-
-
Cordan, B.1
-
103
-
-
0033886799
-
A Single Chip, 1.6Billion, 16b MAC/s Multiprocessor DSP
-
March
-
Ackland B., et al. A Single Chip, 1.6Billion, 16b MAC/s Multiprocessor DSP. IEEE Journal of Solid State Circuits March 2000, vol. 35(no. 3).
-
(2000)
IEEE Journal of Solid State Circuits
, vol.35
, Issue.3
-
-
Ackland, B.1
-
104
-
-
84882845141
-
-
August, Scientific American
-
Agrawal A. Raw Computation August 1999, Scientific American.
-
(1999)
Raw Computation
-
-
Agrawal, A.1
-
106
-
-
0038645161
-
An 800 MHz Starconnected On-chip Network for Application to Systems On a Chip
-
Lee S.Y., Song S.J., Lee K., Woo J.H., Kim S.E., Nam B.G., Yoo H.J. An 800 MHz Starconnected On-chip Network for Application to Systems On a Chip. IEEE Solid State Circuits Conference 2003, 468-469.
-
(2003)
IEEE Solid State Circuits Conference
, pp. 468-469
-
-
Lee, S.Y.1
Song, S.J.2
Lee, K.3
Woo, J.H.4
Kim, S.E.5
Nam, B.G.6
Yoo, H.J.7
-
108
-
-
0034245046
-
Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise
-
August
-
Hegde R., Shanbhag N. Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise. IEEE Transactions on VLSI Systems August 2000, (no. 4):379-391.
-
(2000)
IEEE Transactions on VLSI Systems
, Issue.4
, pp. 379-391
-
-
Hegde, R.1
Shanbhag, N.2
-
111
-
-
0344981523
-
Xpipes: A Latency Insensitive Parameterized Network-on-chip Architecture for Multiprocessor SoCs
-
Dall'Osso M., Biccari G., Giovannini L., Bertozzi D., Benini L. Xpipes: A Latency Insensitive Parameterized Network-on-chip Architecture for Multiprocessor SoCs. International Conference on Computer Design 2003, 536-539.
-
(2003)
International Conference on Computer Design
, pp. 536-539
-
-
Dall'Osso, M.1
Biccari, G.2
Giovannini, L.3
Bertozzi, D.4
Benini, L.5
-
116
-
-
84948696213
-
A Network on Chip Architecture and Design Methodology
-
April
-
Kumar S., Jantsch A., Soininen J., Forsell M., Millberg M., oberg J., Tiensyrj K., Hemani A. A Network on Chip Architecture and Design Methodology. Proceedings of IEEE Computer Society Annual Symposium on VLSI April 2002, 105-112.
-
(2002)
Proceedings of IEEE Computer Society Annual Symposium on VLSI
, pp. 105-112
-
-
Kumar, S.1
Jantsch, A.2
Soininen, J.3
Forsell, M.4
Millberg, M.5
oberg, J.6
Tiensyrj, K.7
Hemani, A.8
-
119
-
-
0034841440
-
Micro Network Based Integration, for SOCs
-
Wingard D. Micro Network Based Integration, for SOCs. Design Automation Conference 2001, 673-677.
-
(2001)
Design Automation Conference
, pp. 673-677
-
-
Wingard, D.1
-
120
-
-
0034853719
-
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
-
Lahiri K., Raghunathan A., Lakshminarayana G. LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. Design Automation Conference 2001, 15-20.
-
(2001)
Design Automation Conference
, pp. 15-20
-
-
Lahiri, K.1
Raghunathan, A.2
Lakshminarayana, G.3
-
125
-
-
0036709408
-
Virtual Benchmarking and Model continuity in Prototyping Embedded Multiprocessor Signal Processing Systems
-
Sept
-
Janka R., Willis L., Baumstark L. Virtual Benchmarking and Model continuity in Prototyping Embedded Multiprocessor Signal Processing Systems. IEEE Transaction onf Software Engineering Sept. 2002, vol. 28(no. 9):836-846.
-
(2002)
IEEE Transaction onf Software Engineering
, vol.28
, Issue.9
, pp. 836-846
-
-
Janka, R.1
Willis, L.2
Baumstark, L.3
-
128
-
-
0343462222
-
Data Memory Organization and Optimition in Applicationspecific Systems
-
Panda R., Dutt N., Nicolau A., Catthoor F., Vandercappelle A., Brockmeyer E., Kulkarni C., De Greef E. Data Memory Organization and Optimition in Applicationspecific Systems. IEEE Design & Test of Computers May June 2002, Vol.18(no. 3):5658.
-
(2002)
IEEE Design & Test of Computers
, vol.18
, Issue.3
, pp. 5658
-
-
Panda, R.1
Dutt, N.2
Nicolau, A.3
Catthoor, F.4
Vandercappelle, A.5
Brockmeyer, E.6
Kulkarni, C.7
De Greef, E.8
-
131
-
-
85008048480
-
Automatic Generation and Targeting of Application-specific Operating Systems and Embedded Systemes Software
-
Gauthier L., Yoo S., Jerraya A. Automatic Generation and Targeting of Application-specific Operating Systems and Embedded Systemes Software. IEEE Computer Aided Design of Integrated Circuits and Systems Nov. 2001, vol. 20(no. 11):1293-1301.
-
(2001)
IEEE Computer Aided Design of Integrated Circuits and Systems
, vol.20
, Issue.11
, pp. 1293-1301
-
-
Gauthier, L.1
Yoo, S.2
Jerraya, A.3
-
132
-
-
0035283970
-
The Rationale for Distributed Semantics as a Topology Independent System Design Methodology and Its Implementation In the Virtuoso RTOS
-
Verhulst E The Rationale for Distributed Semantics as a Topology Independent System Design Methodology and Its Implementation In the Virtuoso RTOS. Design Automation for Embedded Systems 2002, vol. 6:277-294.
-
(2002)
Design Automation for Embedded Systems
, vol.6
, pp. 277-294
-
-
Verhulst, E.1
-
135
-
-
0003913538
-
-
Kluwer
-
Catthoor F., Wuytack S., De Greef E., Balasa F., Nachtergaele L., Vandecappelle A. Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design 1998, Kluwer.
-
(1998)
Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design
-
-
Catthoor, F.1
Wuytack, S.2
De Greef, E.3
Balasa, F.4
Nachtergaele, L.5
Vandecappelle, A.6
-
136
-
-
0034843014
-
VSIPL: An Object-based Open Standard API for Vector, Signal and Image Processing
-
Janka R., Judd R., Lebak J., Richards M., Campbell D. VSIPL: An Object-based Open Standard API for Vector, Signal and Image Processing. IEEE Conference on Acoustic, Speech and Signal Processing 2001, 949-952.
-
(2001)
IEEE Conference on Acoustic, Speech and Signal Processing
, pp. 949-952
-
-
Janka, R.1
Judd, R.2
Lebak, J.3
Richards, M.4
Campbell, D.5
-
138
-
-
0036402011
-
SystemC Co-Simulation of Multi-Processor Systems-on-Chip
-
Benini L., Bertozzi D., Bruni D., Drago N., Fummi F., Poncino M. SystemC Co-Simulation of Multi-Processor Systems-on-Chip. IEEE International Conference on Computer Design 2002, 494-499.
-
(2002)
IEEE International Conference on Computer Design
, pp. 494-499
-
-
Benini, L.1
Bertozzi, D.2
Bruni, D.3
Drago, N.4
Fummi, F.5
Poncino, M.6
-
139
-
-
0004670755
-
Advances and Future Challenges in Binary Translation and Optimization
-
no. 11
-
Altman E., Ebcioglu K., Gachwind M., Sathaye S. Advances and Future Challenges in Binary Translation and Optimization. Proceedings of the IEEE Nov. 2001, vol. 89:1710-1722. no. 11.
-
(2001)
Proceedings of the IEEE
, vol.89
, pp. 1710-1722
-
-
Altman, E.1
Ebcioglu, K.2
Gachwind, M.3
Sathaye, S.4
-
142
-
-
84882842321
-
Transmeta's Crusoe: Cool Chips for Mobile Computing
-
Ditzel D. Transmeta's Crusoe: Cool Chips for Mobile Computing. Hot Chips Symposium 2000.
-
(2000)
Hot Chips Symposium
-
-
Ditzel, D.1
-
143
-
-
0022141776
-
Fattrees: Universal Networks for Hardware Efficient Supercomputing
-
Leiserson C. Fattrees: Universal Networks for Hardware Efficient Supercomputing. IEEE Transactions on Computers October 1985, vol. 34(no. 10):892-901.
-
(1985)
IEEE Transactions on Computers
, vol.34
, Issue.10
, pp. 892-901
-
-
Leiserson, C.1
-
144
-
-
0030285348
-
160MHz, 32b, 0.5W CMOS RISC Microprocessor
-
Montanaro J.A., et al. 160MHz, 32b, 0.5W CMOS RISC Microprocessor. IEEE Journal of Solid-State Circuits Nov. 1996, vol. 31(no. 11):1703-1714.
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, Issue.11
, pp. 1703-1714
-
-
Montanaro, J.A.1
-
145
-
-
0034314477
-
1V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital Signal Processing
-
Zhang H., Prabhu V., George V., Wan M., Benes M., Abnous A., Rabaey J.A. 1V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital Signal Processing. IEEE Journal of Solid-State Circuits Nov. 2000, vol. 35(no. 11):1697-1704.
-
(2000)
IEEE Journal of Solid-State Circuits
, vol.35
, Issue.11
, pp. 1697-1704
-
-
Zhang, H.1
Prabhu, V.2
George, V.3
Wan, M.4
Benes, M.5
Abnous, A.6
Rabaey, J.A.7
-
148
-
-
0038345691
-
Virtual Simple Architecture: Exceeding the Complexity Limit in Safe Real-time Systems
-
Anantaraman A., Seth K., Patil K., Rotenberg E., Mueller F. Virtual Simple Architecture: Exceeding the Complexity Limit in Safe Real-time Systems. Proceedings of the 30th International Symposium on Computer Architecture July 2003, 350-361.
-
(2003)
Proceedings of the 30th International Symposium on Computer Architecture
, pp. 350-361
-
-
Anantaraman, A.1
Seth, K.2
Patil, K.3
Rotenberg, E.4
Mueller, F.5
-
149
-
-
0002017307
-
Instruction-level Parallel Processing: History, Overview, and Perspective
-
Rau B.R., Fisher J.A. Instruction-level Parallel Processing: History, Overview, and Perspective. Journal of Supercomputing, Special Issue July 1993, 7:9-50.
-
(1993)
Journal of Supercomputing, Special Issue
, vol.7
, pp. 9-50
-
-
Rau, B.R.1
Fisher, J.A.2
-
153
-
-
84882852652
-
A Methodology for Study of Network Processing Architectures
-
North Carolina State University
-
Suryanarayanan D. A Methodology for Study of Network Processing Architectures. MS Thesis July 2001, North Carolina State University.
-
(2001)
MS Thesis
-
-
Suryanarayanan, D.1
-
157
-
-
0039436443
-
Reduced Instruction Set Computer Architectures for VLSI
-
University of California, Berkeley, CA
-
Katevenis M.G.H. Reduced Instruction Set Computer Architectures for VLSI. CS Division Report No. UCB/CSD 83/141 October 1983, University of California, Berkeley, CA.
-
(1983)
CS Division Report No. UCB/CSD 83/141
-
-
Katevenis, M.G.H.1
-
158
-
-
0021817378
-
A Reduced Instruction Set Computers
-
Patterson D. A Reduced Instruction Set Computers. CACM January 1985, 28(1):8-21.
-
(1985)
CACM
, vol.28
, Issue.1
, pp. 8-21
-
-
Patterson, D.1
-
159
-
-
0040621752
-
The MIPS machine
-
Hennessy J., Jouppi N., Gill J., Baskett F., Strong A., Gross T., Rowen C., Leonard J. The MIPS machine. Proceedings of the IEEE Compcon February 1982, 2-7.
-
(1982)
Proceedings of the IEEE Compcon
, pp. 2-7
-
-
Hennessy, J.1
Jouppi, N.2
Gill, J.3
Baskett, F.4
Strong, A.5
Gross, T.6
Rowen, C.7
Leonard, J.8
-
160
-
-
0003278283
-
The Microarchitecture of the Pentiumò 4 Processor
-
Hinton G., Sager D., Upton M., Boggs D., Carmean D., Kyker A., Roussel P. The Microarchitecture of the Pentiumò 4 Processor. Intel Technology Journal, 1st Quarter 2001.
-
(2001)
Intel Technology Journal, 1st Quarter
-
-
Hinton, G.1
Sager, D.2
Upton, M.3
Boggs, D.4
Carmean, D.5
Kyker, A.6
Roussel, P.7
-
161
-
-
0036298603
-
POWER4 System Microarchitecture
-
Tendler J.M., Dodson J.S., Fields J.S., Le H., Sinharoy B. POWER4 System Microarchitecture. IBM Journal of Research and Development January 2002, 46(1):5-25.
-
(2002)
IBM Journal of Research and Development
, vol.46
, Issue.1
, pp. 5-25
-
-
Tendler, J.M.1
Dodson, J.S.2
Fields, J.S.3
Le, H.4
Sinharoy, B.5
-
167
-
-
0026918390
-
Improving the accuracy of dynamic branch prediction using branch correlation
-
Pan S., So K., Rahmeh J.T. Improving the accuracy of dynamic branch prediction using branch correlation. ACM Computer Architecture News October 1992, vol. 20:76-84.
-
(1992)
ACM Computer Architecture News
, vol.20
, pp. 76-84
-
-
Pan, S.1
So, K.2
Rahmeh, J.T.3
-
169
-
-
0021204160
-
Branch prediction strategies and branch target buffer design
-
Lee J.K.F., Smith A.J. Branch prediction strategies and branch target buffer design. IEEE Computer January 1984, vol. 17(1):6-22.
-
(1984)
IEEE Computer
, vol.17
, Issue.1
, pp. 6-22
-
-
Lee, J.K.F.1
Smith, A.J.2
-
170
-
-
0003158656
-
Hitting the Memory Wall: Implications of the Obvious
-
Wulf W.A., McKee S.A. Hitting the Memory Wall: Implications of the Obvious. Computer Architecture News March 1995, 23(1):20-24.
-
(1995)
Computer Architecture News
, vol.23
, Issue.1
, pp. 20-24
-
-
Wulf, W.A.1
McKee, S.A.2
-
171
-
-
0029666641
-
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
-
Tullsen D.M., Eggers S.J., Emer J.S., Levy H.M., Lo J.L., Stamm R.L. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. Proceedings of the 23rd Annual International symposium on Computer Architecture May 1996.
-
(1996)
Proceedings of the 23rd Annual International symposium on Computer Architecture
-
-
Tullsen, D.M.1
Eggers, S.J.2
Emer, J.S.3
Levy, H.M.4
Lo, J.L.5
Stamm, R.L.6
-
172
-
-
0020289466
-
Architecture and applications of the HEP multiprocessor computer system
-
Smith B.J. Architecture and applications of the HEP multiprocessor computer system. SPIE Real-Time Signal Processing IV August 1981, 241-248.
-
(1981)
SPIE Real-Time Signal Processing IV
, pp. 241-248
-
-
Smith, B.J.1
-
175
-
-
0031199614
-
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
-
Lo J.L., Eggers S.J., Emer J.S., Levy R., Stamm R.M., Tullsen D.M. Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading. ACM Transactions on Computer Systems 1997, 15(3):322-354.
-
(1997)
ACM Transactions on Computer Systems
, vol.15
, Issue.3
, pp. 322-354
-
-
Lo, J.L.1
Eggers, S.J.2
Emer, J.S.3
Levy, R.4
Stamm, R.M.5
Tullsen, D.M.6
-
176
-
-
84882865873
-
-
http://www.arm.com/markets.
-
-
-
-
177
-
-
84882880441
-
The Ubicom IP3023 Wireless Network Processor
-
Ubicom
-
Ubicom The Ubicom IP3023 Wireless Network Processor. White Paper April 2003, http://www.ubicom.com/pdfs/products/ip3000/processor/WP-IP3023WNP.
-
(2003)
White Paper
-
-
-
178
-
-
84882928155
-
-
http://www.arm.com/arm/documentation.
-
-
-
-
179
-
-
84882929491
-
-
http://www.arm.com/armtech/ARM10_Thumb.
-
-
-
-
180
-
-
84882918777
-
-
http://www.arm.com/armtech/ARM11.
-
-
-
-
181
-
-
84882847550
-
-
http://www.arm.com/armtech/ARM7_Thumb.
-
-
-
-
182
-
-
84882882420
-
-
http://www.arm.com/armtech/ARM9_Thumb.
-
-
-
-
183
-
-
84882916019
-
-
http://www.arm.com/armtech/ARM9E_Thumb.
-
-
-
-
186
-
-
84882837787
-
-
http://www-3.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_440_Embe dded_Core.
-
-
-
-
187
-
-
84882819126
-
-
http://www.mips.com/content/PressRoom/PressKits/files/mips32_24k.pdf.
-
-
-
-
191
-
-
0025028257
-
The Tera Computer System
-
Alverson R., Callahan D., Cummings D., Koblenz B., Porterfield A., Smith B. The Tera Computer System. Proceedings of the International Conference on Supercomputing June 1990, 1-6.
-
(1990)
Proceedings of the International Conference on Supercomputing
, pp. 1-6
-
-
Alverson, R.1
Callahan, D.2
Cummings, D.3
Koblenz, B.4
Porterfield, A.5
Smith, B.6
-
195
-
-
0003039244
-
An accurate worst case timing analysis for RISC processors
-
Lim S-S., Bae Y.H., Jang T., Rhee B-D., Min L., Park C.Y., Shin H., Kim C.S. An accurate worst case timing analysis for RISC processors. IEEE Real-Time Systems Symposium December 1994, 97-108.
-
(1994)
IEEE Real-Time Systems Symposium
, pp. 97-108
-
-
Lim, S.-S.1
Bae, Y.H.2
Jang, T.3
Rhee, B.-D.4
Min, L.5
Park, C.Y.6
Shin, H.7
Kim, C.S.8
-
196
-
-
0029546911
-
Efficient microarchitecture, modeling and path analysis for real-time software
-
Li Y-T.S., Malik S., Wolfe A. Efficient microarchitecture, modeling and path analysis for real-time software. IEEE Real-Time Systems Symposium December 1995, 298-397.
-
(1995)
IEEE Real-Time Systems Symposium
, pp. 298-397
-
-
Li, Y.-T.S.1
Malik, S.2
Wolfe, A.3
-
197
-
-
0030414718
-
Cache modeling for real-time software: Beyond direct mapped instruction caches
-
Li Y-T.S., Malik S., Wolfe A. Cache modeling for real-time software: Beyond direct mapped instruction caches. IEEE Real-Time Systems Symposium December 1996, 254-263.
-
(1996)
IEEE Real-Time Systems Symposium
, pp. 254-263
-
-
Li, Y.-T.S.1
Malik, S.2
Wolfe, A.3
-
198
-
-
0033732401
-
Timing analysis for instruction caches
-
Mueller F. Timing analysis for instruction caches. Real-Time Systems May 2000, 18(2/3):209-239.
-
(2000)
Real-Time Systems
, vol.18
, Issue.2-3
, pp. 209-239
-
-
Mueller, F.1
-
199
-
-
0035659264
-
Use of modern processors in safety critical applications
-
Bate I., Conmy P., Kelly T., McDermid J. Use of modern processors in safety critical applications. The Computer Journal 2002, 44(6):531-543.
-
(2002)
The Computer Journal
, vol.44
, Issue.6
, pp. 531-543
-
-
Bate, I.1
Conmy, P.2
Kelly, T.3
McDermid, J.4
-
202
-
-
84882918075
-
TM core
-
TM core. White Paper September 2000, http://www.arm.com/pdfs/comparison-arm7.
-
(2000)
White Paper
-
-
-
203
-
-
84882902954
-
TM microarchitecture
-
TM microarchitecture. White Paper April 2002, http://www.arm.com/pdfs/ARM11%20Microarchitecture%20White%20Paper.pdf.
-
(2002)
White Paper
-
-
-
206
-
-
84858552275
-
Chip industry tackles escalating mask costs
-
Wilson R. Chip industry tackles escalating mask costs. Electronic Engineering Times June 17, 2002.
-
(2002)
Electronic Engineering Times
-
-
Wilson, R.1
-
207
-
-
0003552056
-
-
Semiconductor Industry Association, San Jose, California, L. Wilson (Ed.)
-
The National Technology Roadmap for Semiconductors 1997, Semiconductor Industry Association, San Jose, California. L. Wilson (Ed.).
-
(1997)
The National Technology Roadmap for Semiconductors
-
-
-
209
-
-
84882896490
-
-
http://gcc.gnu.org.
-
-
-
-
214
-
-
84882824782
-
-
http://www.arc.com.
-
-
-
-
218
-
-
84882929804
-
Configurable and Extensible Processors Change System Design
-
Gonzalez R. Configurable and Extensible Processors Change System Design. Hot Chips 1999, 11.
-
(1999)
Hot Chips
, vol.11
-
-
Gonzalez, R.1
-
219
-
-
84882819822
-
-
http://www.eembc.org.
-
-
-
-
220
-
-
84882887841
-
-
http://www.arm.com.
-
-
-
-
221
-
-
84882848346
-
-
http://www.necel.com.
-
-
-
-
222
-
-
84882816536
-
-
http://www.mips.com.
-
-
-
-
223
-
-
84882914804
-
-
http://www.semiconductors.philips.com.
-
-
-
-
224
-
-
84882820442
-
-
http://www.st.com.
-
-
-
-
225
-
-
84882820941
-
-
http://www.st.com.
-
-
-
-
226
-
-
84882823447
-
-
http://www.mentor.com/seamless.
-
-
-
-
229
-
-
0003840779
-
-
Kluwer Academic Publishers
-
Chang H., Cooke L., Hunt M., Martin G., McNelly A., Todd L. Surviving the SOC Revolution-A Guide to Platform-Based Design 1999, Kluwer Academic Publishers.
-
(1999)
Surviving the SOC Revolution-A Guide to Platform-Based Design
-
-
Chang, H.1
Cooke, L.2
Hunt, M.3
Martin, G.4
McNelly, A.5
Todd, L.6
-
230
-
-
84882866092
-
-
http://www.semiconductors.philips.com/platforms/nexperia.
-
-
-
-
231
-
-
14244255204
-
The Philips Nexperia Digital Video Platform
-
Kluwer Academic Publishers, G. Martin, H. Chang (Eds.)
-
de Oliveira J.A., van Antwerpen H. The Philips Nexperia Digital Video Platform. Winning the SoC Revolution 2003, 67-96. Kluwer Academic Publishers. G. Martin, H. Chang (Eds.).
-
(2003)
Winning the SoC Revolution
, pp. 67-96
-
-
de Oliveira, J.A.1
van Antwerpen, H.2
-
232
-
-
0035444259
-
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
-
Dutta S., Jensen R., Rieckmann A. Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems. IEEE Design and Test of Computers Sep.-Oct. 2001, 21-31.
-
(2001)
IEEE Design and Test of Computers
, pp. 21-31
-
-
Dutta, S.1
Jensen, R.2
Rieckmann, A.3
-
234
-
-
0028418313
-
Holistic Schedulability for Distributed Hard Real-Time Systems
-
Tindell K., Clark J. Holistic Schedulability for Distributed Hard Real-Time Systems. Euromicro Journal 1994, vol. 40:117-134.
-
(1994)
Euromicro Journal
, vol.40
, pp. 117-134
-
-
Tindell, K.1
Clark, J.2
-
235
-
-
2442559824
-
Mentor Graphics, Seamless Co-Verification Environment
-
Mentor Graphics, Seamless Co-Verification Environment http://www.mentor.com/seamless.
-
-
-
-
236
-
-
84882927464
-
Axys Design Automation, MaxSim Developer Suite
-
Axys Design Automation, MaxSim Developer Suite http://www.axysdesign.com.
-
-
-
-
237
-
-
0032630848
-
Methodology and technology for virtual component driven hardware/software co-design on the system-level
-
Krolikoski S., Schirrmeister F., Salefski B., Rowson J., Martin G. Methodology and technology for virtual component driven hardware/software co-design on the system-level. IEEE International Symposium on Circuits and Systems ISCAS '99 June 1999, 456-459.
-
(1999)
IEEE International Symposium on Circuits and Systems ISCAS '99
, pp. 456-459
-
-
Krolikoski, S.1
Schirrmeister, F.2
Salefski, B.3
Rowson, J.4
Martin, G.5
-
238
-
-
84882868220
-
-
AbsInt.Worst Case Execution Time Analyses
-
AbsInt.Worst Case Execution Time Analyses http://www.absint.com/wcet.htm.
-
-
-
-
240
-
-
0032292381
-
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
-
Theiling H., Ferdinand C.H. Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis. Proc. 19th IEEE Real-Time Systems Symposium Dec. 1998, 144-153.
-
(1998)
Proc. 19th IEEE Real-Time Systems Symposium
, pp. 144-153
-
-
Theiling, H.1
Ferdinand, C.H.2
-
244
-
-
84947261898
-
Reliable and Precise WCET Determination for a Real-Life Processor
-
Lake Tahoe, USA, Springer, Embedded Software Workshop
-
Ferdinand C.H., et al. Reliable and Precise WCET Determination for a Real-Life Processor. LNCS 2211 Oct. 2001, 469ff. Lake Tahoe, USA, Springer.
-
(2001)
LNCS 2211
-
-
Ferdinand, C.H.1
-
246
-
-
0029345326
-
An accurate worst case timing analysis for RISC processors
-
Lim S., Bae Y., Jang G., Rhee B., Min S., Park C., Shin H., Park K., Moon S., Kim C. An accurate worst case timing analysis for RISC processors. Transactions on Software Engineering July 1995, 593-604.
-
(1995)
Transactions on Software Engineering
, pp. 593-604
-
-
Lim, S.1
Bae, Y.2
Jang, G.3
Rhee, B.4
Min, S.5
Park, C.6
Shin, H.7
Park, K.8
Moon, S.9
Kim, C.10
-
247
-
-
0032690911
-
Integrating Communication Protocol Selection with Hardware/Software Codesign
-
Knudsen P.V., Madsen J. Integrating Communication Protocol Selection with Hardware/Software Codesign. IEEE Transactions on CAD 8, Aug. 1999, vol. 18:1077-1095.
-
(1999)
IEEE Transactions on CAD
, vol.18
, pp. 1077-1095
-
-
Knudsen, P.V.1
Madsen, J.2
-
250
-
-
0023138886
-
Static scheduling of synchronous data flow programs for digital signal processing
-
Lee E.A., Messerschmitt D.G. Static scheduling of synchronous data flow programs for digital signal processing. IEEE Transactions on Computers Jan. 1987, vol. 36(1):24-35.
-
(1987)
IEEE Transactions on Computers
, vol.36
, Issue.1
, pp. 24-35
-
-
Lee, E.A.1
Messerschmitt, D.G.2
-
252
-
-
84882813314
-
-
Sonics SiliconBackplane MicroNetwork Overview
-
Sonics SiliconBackplane MicroNetwork Overview http://www.sonicsinc.com/sonics/products/siliconbackplane.
-
-
-
-
254
-
-
84974687699
-
Scheduling algorithms for multiprogramming in a hardreal time environment
-
Liu C.L., Layland J.W. Scheduling algorithms for multiprogramming in a hardreal time environment. Journal of the ACM 1973, vol. 20(1):46-61.
-
(1973)
Journal of the ACM
, vol.20
, Issue.1
, pp. 46-61
-
-
Liu, C.L.1
Layland, J.W.2
-
255
-
-
0028207780
-
Generalized Rate-Monotonic Scheduling Theory: A Framework for Developing Real-Time Systems
-
Sha L., Rajkumar R., Sathaye S.S. Generalized Rate-Monotonic Scheduling Theory: A Framework for Developing Real-Time Systems. Proc. of the IEEE 1994, vol. 82:86.
-
(1994)
Proc. of the IEEE
, vol.82
, pp. 86
-
-
Sha, L.1
Rajkumar, R.2
Sathaye, S.S.3
-
256
-
-
0032205482
-
Performance estimation for real-time distributed embedded systems
-
Yen T., Wolf W.H. Performance estimation for real-time distributed embedded systems. IEEE Transactions on Parallel and Distributed Systems Nov. 1998, vol. 9(11):1125-1136.
-
(1998)
IEEE Transactions on Parallel and Distributed Systems
, vol.9
, Issue.11
, pp. 1125-1136
-
-
Yen, T.1
Wolf, W.H.2
-
257
-
-
84880911285
-
Fixed priority scheduling of periodic task sets with arbitrary deadlines
-
Lehoczky J. Fixed priority scheduling of periodic task sets with arbitrary deadlines. Proc. Real-Time Systems Symposium 1990, 201-209.
-
(1990)
Proc. Real-Time Systems Symposium
, pp. 201-209
-
-
Lehoczky, J.1
-
258
-
-
0000703331
-
Applying new scheduling theory to static priority preemptive scheduling
-
Audsley N.C., Burns A., Richardson M.F., Tindell K., Wellings A.J. Applying new scheduling theory to static priority preemptive scheduling. Journal of Real-Time Systems 1993, vol. 8(5):284-292.
-
(1993)
Journal of Real-Time Systems
, vol.8
, Issue.5
, pp. 284-292
-
-
Audsley, N.C.1
Burns, A.2
Richardson, M.F.3
Tindell, K.4
Wellings, A.J.5
-
264
-
-
0033682521
-
Real-time Calculus For Scheduling Hard Real-Time Systems
-
Thiele L., Chakraborty S., Naedele M. Real-time Calculus For Scheduling Hard Real-Time Systems. International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland March 2000, vol. 4:101-104.
-
(2000)
International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland
, vol.4
, pp. 101-104
-
-
Thiele, L.1
Chakraborty, S.2
Naedele, M.3
-
268
-
-
0345382714
-
A Formal Approach to MpSoC Performance Verification
-
Richter K., Jersak M., Ernst R. A Formal Approach to MpSoC Performance Verification. IEEE Computer April 2003, vol. 36(4):60-67.
-
(2003)
IEEE Computer
, vol.36
, Issue.4
, pp. 60-67
-
-
Richter, K.1
Jersak, M.2
Ernst, R.3
-
270
-
-
84882911973
-
-
http://www.spi-project.org.
-
-
-
-
271
-
-
33947637241
-
Hardware/software codesign of embedded systems-The SPI Workbench
-
Ernst R., Ziegenbein D., Richter K., Thiele L., Teich J. Hardware/software codesign of embedded systems-The SPI Workbench. Proc. IEEE Workshop on VLSI June 1999, 9-17.
-
(1999)
Proc. IEEE Workshop on VLSI
, pp. 9-17
-
-
Ernst, R.1
Ziegenbein, D.2
Richter, K.3
Thiele, L.4
Teich, J.5
-
272
-
-
0028396945
-
An Extendible Approach for Analysing Fixed Priority Hard Real-Time Systems
-
Tindell K. An Extendible Approach for Analysing Fixed Priority Hard Real-Time Systems. Journal of Real-Time Systems 1994, vol. 6(2):133-152.
-
(1994)
Journal of Real-Time Systems
, vol.6
, Issue.2
, pp. 133-152
-
-
Tindell, K.1
-
273
-
-
0036705175
-
SPI-a system model for heterogeneously specified embedded systems
-
Ziegenbein D., Richter K., Ernst R., Thiele L., Teich J. SPI-a system model for heterogeneously specified embedded systems. IEEE Transactions Very Large Scale Integration (VLSI) Systems 2002, 379-389.
-
(2002)
IEEE Transactions Very Large Scale Integration (VLSI) Systems
, pp. 379-389
-
-
Ziegenbein, D.1
Richter, K.2
Ernst, R.3
Thiele, L.4
Teich, J.5
-
274
-
-
0034848112
-
Route Packets Not Wires: On-Chip Inter-connection Networks
-
Dally W.J., Towles B. Route Packets Not Wires: On-Chip Inter-connection Networks. Proc Design Automation Conf. June 2001, 684-689.
-
(2001)
Proc Design Automation Conf.
, pp. 684-689
-
-
Dally, W.J.1
Towles, B.2
-
276
-
-
0033903824
-
A Global Wiring Paradigm for Deep Submicron Design
-
Sylvester D., Keutzer K. A Global Wiring Paradigm for Deep Submicron Design. IEEE Trans Computer-aided Design Feb. 2000, vol. 19:242-252.
-
(2000)
IEEE Trans Computer-aided Design
, vol.19
, pp. 242-252
-
-
Sylvester, D.1
Keutzer, K.2
-
277
-
-
84882876070
-
-
OMI 324 PI Bus, Rev 0. 3d. OMI Standards Draft, 1994 Siemens AG.
-
OMI 324 PI Bus, Rev 0. 3d. OMI Standards Draft, 1994 Siemens AG.
-
-
-
-
278
-
-
84882852223
-
AMBA 2.0 Specification
-
AMBA 2.0 Specification http://www.arm.com/armtech/AMBA.
-
-
-
-
279
-
-
84882911550
-
-
CoreConnect Bus Architecture
-
CoreConnect Bus Architecture http://www.chips.ibm.com/products/coreconnect.
-
-
-
-
280
-
-
0031998264
-
Architectural Choices in Large Scale ATM Switches
-
Turner J., Yamanaka N. Architectural Choices in Large Scale ATM Switches. IEICE Trans on Communications Feb. 1998, vol. E-81B:120-137.
-
(1998)
IEICE Trans on Communications
, vol.E-81B
, pp. 120-137
-
-
Turner, J.1
Yamanaka, N.2
-
281
-
-
84859967419
-
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
-
Adriahantenaina A., Charlery H., Greiner A., Mortiez L., Zeferino C.A. SPIN: A Scalable, Packet Switched, On-Chip Micro-Network. Proc Design Automation & Test Europe (DATE) Conf. 2003, 70-73.
-
(2003)
Proc Design Automation & Test Europe (DATE) Conf.
, pp. 70-73
-
-
Adriahantenaina, A.1
Charlery, H.2
Greiner, A.3
Mortiez, L.4
Zeferino, C.A.5
-
282
-
-
0036760592
-
An Interconnect Architecture for Networking System-on-Chips
-
Karim F., Nguyen A., Dey S. An Interconnect Architecture for Networking System-on-Chips. IEEE Micro Oct. 2002, vol. 22:36-45.
-
(2002)
IEEE Micro
, vol.22
, pp. 36-45
-
-
Karim, F.1
Nguyen, A.2
Dey, S.3
-
283
-
-
84882823584
-
-
Crossbow Technologies
-
Crossbow Technologies http://www.crossbowip.com.
-
-
-
-
284
-
-
0004141908
-
-
Prentice Hall, Englewood Cliffs, N.J.
-
Tanenbaum A.S. Computer Networks 1989, Prentice Hall, Englewood Cliffs, N.J.
-
(1989)
Computer Networks
-
-
Tanenbaum, A.S.1
-
285
-
-
0036149420
-
Networks on Chips: A new Paradigm for SoC Design
-
Benini L., Micheli G.D. Networks on Chips: A new Paradigm for SoC Design. IEEE Computer 2002, vol. 35(no. 1):70-78.
-
(2002)
IEEE Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
Micheli, G.D.2
-
286
-
-
84882825413
-
-
Sonics Integration Architecture.Sonics
-
Sonics Integration Architecture.Sonics http://www.sonicsinc.com.
-
-
-
-
288
-
-
2942575873
-
LOTTERYBUS: A New Communication Architecture for High-Performance System-on-Chip Designs
-
Lahiri K., Lakshminarayana G., Raghunathan A. LOTTERYBUS: A New Communication Architecture for High-Performance System-on-Chip Designs. Proc Design Automation Conf. June 2001, 15-20.
-
(2001)
Proc Design Automation Conf.
, pp. 15-20
-
-
Lahiri, K.1
Lakshminarayana, G.2
Raghunathan, A.3
-
289
-
-
0034428335
-
DS-CDMA Wired Bus With Simple Interconnection Topology for Parallel Processing System LSIs
-
Yoshimura R., Boon K.T., Ogawa T., Hatanaka S., Matsuoka T., Taniguchi K. DS-CDMA Wired Bus With Simple Interconnection Topology for Parallel Processing System LSIs. Proc Int Solid-State Circuits Conf. 2000, 370-371.
-
(2000)
Proc Int Solid-State Circuits Conf.
, pp. 370-371
-
-
Yoshimura, R.1
Boon, K.T.2
Ogawa, T.3
Hatanaka, S.4
Matsuoka, T.5
Taniguchi, K.6
-
291
-
-
0036911588
-
A Hierarchical Modeling Framework for On-Chip Communication Architectures
-
Zhu X., Malik S. A Hierarchical Modeling Framework for On-Chip Communication Architectures. Proc Int Conf Computer-Aided Design Nov. 2002.
-
(2002)
Proc Int Conf Computer-Aided Design
-
-
Zhu, X.1
Malik, S.2
-
292
-
-
84882848785
-
Virtual Component Interface Standard Version 2
-
Virtual Component Interface Standard Version 2 http://www.vsia.org/resources/VSIAStandards.htm.
-
-
-
-
293
-
-
84882436917
-
Open Core Protocol International Partnership (OCP-IP)
-
Open Core Protocol International Partnership (OCP-IP) http://www.ocpip.org.
-
-
-
-
297
-
-
0034826750
-
A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design
-
Yoo S., Nicolescu G., Lyonnard D., Baghadi A., Jerraya A.A. A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design. Proc International Symposium on Hardware/Software Codesign Apr. 2001, 195-200.
-
(2001)
Proc International Symposium on Hardware/Software Codesign
, pp. 195-200
-
-
Yoo, S.1
Nicolescu, G.2
Lyonnard, D.3
Baghadi, A.4
Jerraya, A.A.5
-
298
-
-
0034854046
-
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip
-
Lyonnard D., Yoo S., Baghdadi A., Jerraya A.A. Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. Proc Design Automation Conf. June 2001, 518-523.
-
(2001)
Proc Design Automation Conf.
, pp. 518-523
-
-
Lyonnard, D.1
Yoo, S.2
Baghdadi, A.3
Jerraya, A.A.4
-
301
-
-
0031634246
-
A Framework for Estimating and Minimizing the Energy Dissipation of HW/SW Embedded Systems
-
Li Y., Henkel J. A Framework for Estimating and Minimizing the Energy Dissipation of HW/SW Embedded Systems. Proc Design Automation Conf. June 1998, 188-193.
-
(1998)
Proc Design Automation Conf.
, pp. 188-193
-
-
Li, Y.1
Henkel, J.2
-
303
-
-
0036625242
-
Co-Simulation Based Power Estimation for System-on-Chip Design
-
Lajolo M., Raghunathan A., Dey S., Lavagno L., Sangiovanni-Vincentelli A. Co-Simulation Based Power Estimation for System-on-Chip Design. IEEE Trans VLSI Systems June 2002, vol. 10:253-266.
-
(2002)
IEEE Trans VLSI Systems
, vol.10
, pp. 253-266
-
-
Lajolo, M.1
Raghunathan, A.2
Dey, S.3
Lavagno, L.4
Sangiovanni-Vincentelli, A.5
-
304
-
-
0029547607
-
Communication Synthesis for Distributed Embedded Systems
-
Yen T., Wolf W. Communication Synthesis for Distributed Embedded Systems. Proc Int Conf Computer-Aided Deisgn Nov. 1995, 288-294.
-
(1995)
Proc Int Conf Computer-Aided Deisgn
, pp. 288-294
-
-
Yen, T.1
Wolf, W.2
-
306
-
-
0031335038
-
Performance Analysis of a System of Communicating Processes
-
Dey S., Bommu S. Performance Analysis of a System of Communicating Processes. Proc Int Conf Computer-Aided Design Nov. 1997, 590-597.
-
(1997)
Proc Int Conf Computer-Aided Design
, pp. 590-597
-
-
Dey, S.1
Bommu, S.2
-
307
-
-
84882307693
-
Integrating Communication Protocol Selection with Partitioning in Hard-ware/Software Codesign
-
Knudsen P., Madsen J. Integrating Communication Protocol Selection with Partitioning in Hard-ware/Software Codesign. Proc Int Symp System Level Synthesis Dec. 1998, 111-116.
-
(1998)
Proc Int Symp System Level Synthesis
, pp. 111-116
-
-
Knudsen, P.1
Madsen, J.2
-
310
-
-
0030644938
-
System-Level Synthesis of Low-Power Hard Real-Time Systems
-
Kirovski D., Potkonjak M. System-Level Synthesis of Low-Power Hard Real-Time Systems. Proc Design Automation Conf. June 1997, 697-702.
-
(1997)
Proc Design Automation Conf.
, pp. 697-702
-
-
Kirovski, D.1
Potkonjak, M.2
-
312
-
-
0000404969
-
-
J VLSI Signal Processing, Nov
-
Lieverse, P., Wolf, P. V. D., Vissers, K., and Deprettere, E. A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems, in J VLSI Signal Processing, Nov. 2001.
-
(2001)
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems
-
-
Lieverse, P.1
Wolf, P.V.D.2
Vissers, K.3
Deprettere, E.4
-
314
-
-
0035368837
-
System-Level Performance Analysis for Designing On-Chip Communication Architectures
-
Lahiri K., Raghunathan A., Dey S. System-Level Performance Analysis for Designing On-Chip Communication Architectures. IEEE Trans Computer-Aided Design June 2001, vol. 20:768-783.
-
(2001)
IEEE Trans Computer-Aided Design
, vol.20
, pp. 768-783
-
-
Lahiri, K.1
Raghunathan, A.2
Dey, S.3
-
319
-
-
84990479742
-
An Efficient Heuristic Procedure for Partitioning Graphs
-
Kernighan B., Lin S. An Efficient Heuristic Procedure for Partitioning Graphs. Bell Systems Technical Journal 1970, vol. 49:291-307.
-
(1970)
Bell Systems Technical Journal
, vol.49
, pp. 291-307
-
-
Kernighan, B.1
Lin, S.2
-
320
-
-
0033685462
-
Communication Architecture Tuners: A Methodology for the Design of High Performance Communication Architectures for System-on-Chips
-
Lahiri K., Raghunathan A., Lakshminarayana G., Dey S. Communication Architecture Tuners: A Methodology for the Design of High Performance Communication Architectures for System-on-Chips. Proc Design Automation Conf. June 2000, 513-518.
-
(2000)
Proc Design Automation Conf.
, pp. 513-518
-
-
Lahiri, K.1
Raghunathan, A.2
Lakshminarayana, G.3
Dey, S.4
-
321
-
-
0031104154
-
A Partitioning Scheme for Optimizing Interconnect Power
-
Mehra R., Guerra L.M., Rabaey J. A Partitioning Scheme for Optimizing Interconnect Power. IEEE J Solid-State Circuits Mar. 1997, vol. 32:433-443.
-
(1997)
IEEE J Solid-State Circuits
, vol.32
, pp. 433-443
-
-
Mehra, R.1
Guerra, L.M.2
Rabaey, J.3
-
322
-
-
0031342532
-
Low Power Encodings for Global Communication in CMOS VLSI
-
Stan M., Burleson W. Low Power Encodings for Global Communication in CMOS VLSI. IEEE Trans VLSI Systems Dec. 1997, vol. 5:49-58.
-
(1997)
IEEE Trans VLSI Systems
, vol.5
, pp. 49-58
-
-
Stan, M.1
Burleson, W.2
-
323
-
-
0032300757
-
Power Optimization of Core-Based Systems by Address Bus Encoding
-
Benini L., Micheli G.D., Macii E., Pancino M., Quer S. Power Optimization of Core-Based Systems by Address Bus Encoding. IEEE Trans VLSI Systems Dec. 1998, vol. 6:554-562.
-
(1998)
IEEE Trans VLSI Systems
, vol.6
, pp. 554-562
-
-
Benini, L.1
Micheli, G.D.2
Macii, E.3
Pancino, M.4
Quer, S.5
-
325
-
-
0036638793
-
An Interconnect Energy Model Considering Coupling Effects
-
Uchino T., Cong J. An Interconnect Energy Model Considering Coupling Effects. IEEE Trans Computer-Aided Design July 2002, vol. 21:763-776.
-
(2002)
IEEE Trans Computer-Aided Design
, vol.21
, pp. 763-776
-
-
Uchino, T.1
Cong, J.2
-
326
-
-
0034854189
-
Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies
-
Taylor C.N., Dey S., Zhao Y. Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies. Proc Design Automation Conf. June 2001, 754-757.
-
(2001)
Proc Design Automation Conf.
, pp. 754-757
-
-
Taylor, C.N.1
Dey, S.2
Zhao, Y.3
-
328
-
-
0034481268
-
Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Sub-Micron Technologies
-
Sotiriadis P.P., Chandrakasan A.P. Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Sub-Micron Technologies. Proc Int Conf Computer-Aided Design Nov. 2000, 322-327.
-
(2000)
Proc Int Conf Computer-Aided Design
, pp. 322-327
-
-
Sotiriadis, P.P.1
Chandrakasan, A.P.2
-
329
-
-
0034483997
-
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design
-
Kim K.W., Baek K.H., Shanbhag N., Liu C.L., Kang S.M. Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. Proc Int Conf Computer-Aided Design Nov. 2000, 318-321.
-
(2000)
Proc Int Conf Computer-Aided Design
, pp. 318-321
-
-
Kim, K.W.1
Baek, K.H.2
Shanbhag, N.3
Liu, C.L.4
Kang, S.M.5
-
330
-
-
0034841281
-
2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs
-
2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs. Proc Design Automation Conf. June 2001, 744-749.
-
(2001)
Proc Design Automation Conf.
, pp. 744-749
-
-
Henkel, J.1
Lekatsas, H.2
-
331
-
-
13444258261
-
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
-
Henkel J., Lekatsas H. ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. Proc Int Conf VLSI Design Jan. 2002, 113-120.
-
(2002)
Proc Int Conf VLSI Design
, pp. 113-120
-
-
Henkel, J.1
Lekatsas, H.2
-
332
-
-
0034841282
-
Coupling-Driven Bus Design for Low-Power Application-Specific Systems
-
Shin Y., Sakurai T. Coupling-Driven Bus Design for Low-Power Application-Specific Systems. Proc Design Automation Conf. June 2001, 750-753.
-
(2001)
Proc Design Automation Conf.
, pp. 750-753
-
-
Shin, Y.1
Sakurai, T.2
-
335
-
-
0033097604
-
Segmented Bus Design for Low Power
-
Chen J.Y., Jone W.B., Wang J.S., Lu H.I., Chen T.F. Segmented Bus Design for Low Power. IEEE Trans VLSI Systems Mar. 1999, vol. 7:25-29.
-
(1999)
IEEE Trans VLSI Systems
, vol.7
, pp. 25-29
-
-
Chen, J.Y.1
Jone, W.B.2
Wang, J.S.3
Lu, H.I.4
Chen, T.F.5
-
336
-
-
0036540701
-
Architectural Power Optimization by Bus Splitting
-
Hsieh C.-T., Pedram M. Architectural Power Optimization by Bus Splitting. IEEE Trans Computer-Aided Design Apr. 2002, vol. 21:408-414.
-
(2002)
IEEE Trans Computer-Aided Design
, vol.21
, pp. 408-414
-
-
Hsieh, C.-T.1
Pedram, M.2
-
339
-
-
0035007991
-
Battery Life Estimation for Mobile Embedded Systems
-
Panigrahi D., Chiasserini C.F., Dey S., Rao R.R., Raghunathan A., Lahiri K. Battery Life Estimation for Mobile Embedded Systems. Proc Int Conf VLSI Design Jan. 2001, 55-63.
-
(2001)
Proc Int Conf VLSI Design
, pp. 55-63
-
-
Panigrahi, D.1
Chiasserini, C.F.2
Dey, S.3
Rao, R.R.4
Raghunathan, A.5
Lahiri, K.6
-
340
-
-
0027608142
-
Modeling of Galvanostatic Charge and Discharge of Lithium/Polymer/Insertion cell
-
Doyle M., Fuller T.F., Newman J.S. Modeling of Galvanostatic Charge and Discharge of Lithium/Polymer/Insertion cell. J Electrochem Soc June 1993, vol. 140:1526-1533.
-
(1993)
J Electrochem Soc
, vol.140
, pp. 1526-1533
-
-
Doyle, M.1
Fuller, T.F.2
Newman, J.S.3
-
341
-
-
84882875343
-
-
http://www.etsi.org.
-
-
-
-
345
-
-
0032630848
-
Methodology and technology for virtual component-driven hardware/software co-design at the system level
-
Krolikoski S.J., et al. Methodology and technology for virtual component-driven hardware/software co-design at the system level. Proc IEEE Int Symp on Circuits and Systems, ISCAS 99 June 1999.
-
(1999)
Proc IEEE Int Symp on Circuits and Systems, ISCAS 99
-
-
Krolikoski, S.J.1
-
346
-
-
0003652206
-
-
Kluwer Academic Publishers
-
Gajsky D., Zhu J., Domer R., Gerstlauer A., Zhao S. Spec C: Specification language and Methodology 2000, Kluwer Academic Publishers.
-
(2000)
Spec C: Specification language and Methodology
-
-
Gajsky, D.1
Zhu, J.2
Domer, R.3
Gerstlauer, A.4
Zhao, S.5
-
347
-
-
84882809904
-
Architectural Services Modeling for Performance in HW-SW Co-Design
-
Solden S Architectural Services Modeling for Performance in HW-SW Co-Design. Proc SASIMI 2001.
-
(2001)
Proc SASIMI
-
-
Solden, S.1
-
348
-
-
84882838322
-
-
http://www.systemc.org.
-
-
-
-
349
-
-
85072471278
-
Enabling Rapid Design Exploration through Virtual Integration and Simulation of Fault Tolerant Automotive Application
-
Demmeler T., et al. Enabling Rapid Design Exploration through Virtual Integration and Simulation of Fault Tolerant Automotive Application. SAE 2002.
-
(2002)
SAE
-
-
Demmeler, T.1
-
351
-
-
34047186101
-
YAPI: Application Modeling for Signal Processing Systems
-
de Kock E.A., et al. YAPI: Application Modeling for Signal Processing Systems. Proc DAC 2000.
-
(2000)
Proc DAC
-
-
de Kock, E.A.1
-
352
-
-
0000087207
-
The semantics of a simple language for parallel programming
-
North Holland Publishing, Co, L.J. Rosenfeld (Ed.)
-
Kahn G. The semantics of a simple language for parallel programming. Information Proc 1974, North Holland Publishing, Co. L.J. Rosenfeld (Ed.).
-
(1974)
Information Proc
-
-
Kahn, G.1
-
353
-
-
0001325987
-
Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems
-
Buck J.T., et al. Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems. International Journal of Computer Simulation 1994.
-
(1994)
International Journal of Computer Simulation
-
-
Buck, J.T.1
-
360
-
-
0003913538
-
-
Kluwer, Boston
-
Catthoor F., Wuytack S., De Greef E., Balasa F., Nachtergaele L., Vandecappelle A. Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design 1998, Kluwer, Boston.
-
(1998)
Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design
-
-
Catthoor, F.1
Wuytack, S.2
De Greef, E.3
Balasa, F.4
Nachtergaele, L.5
Vandecappelle, A.6
-
362
-
-
0003631973
-
-
Kluwer Academic Publishers, Norwell, MA
-
Panda P.R., Dutt N., Nicolau A. Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration 1999, Kluwer Academic Publishers, Norwell, MA.
-
(1999)
Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration
-
-
Panda, P.R.1
Dutt, N.2
Nicolau, A.3
-
363
-
-
0346048126
-
-
Kluwer Academic Press, Norwell, MA
-
Grun P., Dutt N., Nicolau A. Memory Architecture Exploration for Programmable Embedded Systems 2003, Kluwer Academic Press, Norwell, MA.
-
(2003)
Memory Architecture Exploration for Programmable Embedded Systems
-
-
Grun, P.1
Dutt, N.2
Nicolau, A.3
-
367
-
-
0033076195
-
Augmenting loop tiling with data alignment for improved cache performance
-
Panda P.R., Nakamura H., Dutt N.D., Nicolau A. Augmenting loop tiling with data alignment for improved cache performance. IEEE Transactions on Computers 1999, 48:142-149.
-
(1999)
IEEE Transactions on Computers
, vol.48
, pp. 142-149
-
-
Panda, P.R.1
Nakamura, H.2
Dutt, N.D.3
Nicolau, A.4
-
369
-
-
0034848113
-
Dynamic management of SPM space
-
Kandemir M.T., Ramanujam J., Irwin M.J., Vijaykrishnan N., Kadayif I., Parikh A. Dynamic management of SPM space. Proc. Design Automation Conference 2001, 690-695.
-
(2001)
Proc. Design Automation Conference
, pp. 690-695
-
-
Kandemir, M.T.1
Ramanujam, J.2
Irwin, M.J.3
Vijaykrishnan, N.4
Kadayif, I.5
Parikh, A.6
-
370
-
-
0025429331
-
Improving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers
-
Jouppi N.P. Improving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers. Proc. International Symposium on Computer Architecture 1990, 364-373.
-
(1990)
Proc. International Symposium on Computer Architecture
, pp. 364-373
-
-
Jouppi, N.P.1
-
371
-
-
0031366763
-
Instruction buffering to reduce power in processors for signal processing
-
Bajwa R.S., Hiraki M., Kojima H., Gorny D.J., Nitta K., Shridhar A., Seki K., Sasaki K. Instruction buffering to reduce power in processors for signal processing. IEEE Transactions on VLSI Systems 1997, 5:417-424.
-
(1997)
IEEE Transactions on VLSI Systems
, vol.5
, pp. 417-424
-
-
Bajwa, R.S.1
Hiraki, M.2
Kojima, H.3
Gorny, D.J.4
Nitta, K.5
Shridhar, A.6
Seki, K.7
Sasaki, K.8
-
372
-
-
0033723926
-
Architectural and compiler techniques for energy reduction in high-performance microprocessors
-
Bellas N., Hajj I.N., Polychronopoulos D.C., Stamoulis G. Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Transactions on VLSI Systems 2000, 8:317-326.
-
(2000)
IEEE Transactions on VLSI Systems
, vol.8
, pp. 317-326
-
-
Bellas, N.1
Hajj, I.N.2
Polychronopoulos, D.C.3
Stamoulis, G.4
-
374
-
-
84944312865
-
Compiler-directed management of instruction accesses
-
Chen G., Chen G., Kadayif I., Zhang W., Kandemir M., Kolcu I., Sezer U. Compiler-directed management of instruction accesses. Proc. Euromicro Symposium on Digital System Design, Architectures, Methods and Tools (DSD'03) September, 2003.
-
(2003)
Proc. Euromicro Symposium on Digital System Design, Architectures, Methods and Tools (DSD'03)
-
-
Chen, G.1
Chen, G.2
Kadayif, I.3
Zhang, W.4
Kandemir, M.5
Kolcu, I.6
Sezer, U.7
-
376
-
-
0005408820
-
High-level synthesis with SDRAMs and RAMBUS DRAMs
-
Khare A., Panda P.R., Dutt N.D., Nicolau A. High-level synthesis with SDRAMs and RAMBUS DRAMs. IEICE Transactions on fundamentals of electronics, communications and computer sciences E82-A 1999, 2347-2355.
-
(1999)
IEICE Transactions on fundamentals of electronics, communications and computer sciences E82-A
, pp. 2347-2355
-
-
Khare, A.1
Panda, P.R.2
Dutt, N.D.3
Nicolau, A.4
-
386
-
-
0033279857
-
Minimizing the required memory bandwidth in VLSI system realizations
-
Wuytack S., Catthoor F., Jong G.D., Man H.D. Minimizing the required memory bandwidth in VLSI system realizations. IEEE Transactions on VLSI Systems 1999, 7:433-441.
-
(1999)
IEEE Transactions on VLSI Systems
, vol.7
, pp. 433-441
-
-
Wuytack, S.1
Catthoor, F.2
Jong, G.D.3
Man, H.D.4
-
388
-
-
0030644930
-
Memory-CPU size optimization for embedded system designs
-
Shackleford B., Yasuda M., Okushi E., Koizumi H., Tomiyama H., Yasuura H. Memory-CPU size optimization for embedded system designs. Proc. Design Automation Conference 1997.
-
(1997)
Proc. Design Automation Conference
-
-
Shackleford, B.1
Yasuda, M.2
Okushi, E.3
Koizumi, H.4
Tomiyama, H.5
Yasuura, H.6
-
389
-
-
0346812390
-
Architecture description languages for systems-on-chip design
-
Tomiyama H., Halambi A., Grun P., Dutt N., Nicolau A. Architecture description languages for systems-on-chip design. Proc. 6th Asia Pacific Conference on Chip Design Languages 1999, 109-116.
-
(1999)
Proc. 6th Asia Pacific Conference on Chip Design Languages
, pp. 109-116
-
-
Tomiyama, H.1
Halambi, A.2
Grun, P.3
Dutt, N.4
Nicolau, A.5
-
390
-
-
84904250713
-
Automatic software toolkit generation for embedded systems-on-chip
-
Halambi A., Grun P., Tomiyama H., Dutt N., Nicolau A. Automatic software toolkit generation for embedded systems-on-chip. Proc, ICVC'99 1999.
-
(1999)
Proc, ICVC'99
-
-
Halambi, A.1
Grun, P.2
Tomiyama, H.3
Dutt, N.4
Nicolau, A.5
-
391
-
-
33746967016
-
Data and memory optimization techniques for embedded systems
-
Panda P.R., Catthoor F., Dutt N.D., Danckaert K., Brockmeyer E., Kulkarni C., Vandercappelle A., Kjeldsberg P.G. Data and memory optimization techniques for embedded systems. ACM Transactions on Design Automation of Electronic Systems April 2001, Vol. 6(No. 2).
-
(2001)
ACM Transactions on Design Automation of Electronic Systems
, vol.6
, Issue.2
-
-
Panda, P.R.1
Catthoor, F.2
Dutt, N.D.3
Danckaert, K.4
Brockmeyer, E.5
Kulkarni, C.6
Vandercappelle, A.7
Kjeldsberg, P.G.8
-
392
-
-
84893597192
-
Expression: A language for architecture exploration through compiler/simulator retargetability
-
Halambi A., Grun P., Ganesh V., Khare A., Dutt N., Nicolau A. Expression: A language for architecture exploration through compiler/simulator retargetability. Proc. DATE'99 1999.
-
(1999)
Proc. DATE'99
-
-
Halambi, A.1
Grun, P.2
Ganesh, V.3
Khare, A.4
Dutt, N.5
Nicolau, A.6
-
394
-
-
84882905083
-
Morphable cache architectures: potential benefits
-
Kadayif I., Kandemir M., Vijaykrishnan N., Irwin M.J., Ramanujam J. Morphable cache architectures: potential benefits. Proc. Workshop on Languages, Compilers and Tools for Embedded Systems 2001.
-
(2001)
Proc. Workshop on Languages, Compilers and Tools for Embedded Systems
-
-
Kadayif, I.1
Kandemir, M.2
Vijaykrishnan, N.3
Irwin, M.J.4
Ramanujam, J.5
-
399
-
-
0036045542
-
An integer linear programming based approach for parallelizing applications in on-chip multiprocessors
-
Kadayif I., Kandemir M., Sezer U. An integer linear programming based approach for parallelizing applications in on-chip multiprocessors. Proc. Design Automation Conference June 2002.
-
(2002)
Proc. Design Automation Conference
-
-
Kadayif, I.1
Kandemir, M.2
Sezer, U.3
-
401
-
-
0028409782
-
A singular loop transformation framework based on nonsingular matrices
-
April
-
Li, W., and Pingali, K. A singular loop transformation framework based on nonsingular matrices, International Journal of Parallel Programming, April 22(2):183-205.
-
International Journal of Parallel Programming
, vol.22
, Issue.2
, pp. 183-205
-
-
Li, W.1
Pingali, K.2
-
402
-
-
0003582055
-
Optimizing data locality by array restructuring
-
Computer Science Department, University of Washington, Seattle, WA
-
Leung S.-T., Zahorjan J. Optimizing data locality by array restructuring. Technical Report 1995, Computer Science Department, University of Washington, Seattle, WA.
-
(1995)
Technical Report
-
-
Leung, S.-T.1
Zahorjan, J.2
-
407
-
-
0031988272
-
Tolerating latency in multiprocessors through compiler-inserted prefetching
-
Todd Mowry C. Tolerating latency in multiprocessors through compiler-inserted prefetching. ACM Transactions on Computer Systems February 1998, 16(1):55-92.
-
(1998)
ACM Transactions on Computer Systems
, vol.16
, Issue.1
, pp. 55-92
-
-
Todd Mowry, C.1
-
410
-
-
15844369640
-
Loop transformations for reducing data space requirements of resource-constrained applications
-
Unnikrishnan P., Chen G., Kandemir M., Karakoy M., Kolcu I. Loop transformations for reducing data space requirements of resource-constrained applications. Proc. 10th Annual International Static Analysis Symposium June 11-13, 2003.
-
(2003)
Proc. 10th Annual International Static Analysis Symposium
-
-
Unnikrishnan, P.1
Chen, G.2
Kandemir, M.3
Karakoy, M.4
Kolcu, I.5
-
415
-
-
0034823777
-
Blocking and array contraction across arbitrarily nested loops using affine partitioning
-
Lim A.W., Liao S.-W., Lam S.M. Blocking and array contraction across arbitrarily nested loops using affine partitioning. Proc. ACM SIGPLAN Notices 2001.
-
(2001)
Proc. ACM SIGPLAN Notices
-
-
Lim, A.W.1
Liao, S.-W.2
Lam, S.M.3
-
417
-
-
0003502725
-
-
Kluwer Academci Publishers
-
Catthoor F., Danckaert K., Kulkarni C., Brockmeyer E., Kjeldsberg P.G., Achteren T.V., Omnes T. Data Access and Storage Management for Embedded Programmable Processors 2002, Kluwer Academci Publishers.
-
(2002)
Data Access and Storage Management for Embedded Programmable Processors
-
-
Catthoor, F.1
Danckaert, K.2
Kulkarni, C.3
Brockmeyer, E.4
Kjeldsberg, P.G.5
Achteren, T.V.6
Omnes, T.7
-
425
-
-
0035209061
-
Software-assisted cache replacement mechanisms for embedded systems
-
IEEE
-
Jain P., Devadas S., Engels D., Rudolph L. Software-assisted cache replacement mechanisms for embedded systems. Proceedings, ICCAD'01 2001, IEEE.
-
(2001)
Proceedings, ICCAD'01
-
-
Jain, P.1
Devadas, S.2
Engels, D.3
Rudolph, L.4
-
426
-
-
0033343643
-
Hardware/software co-synthesis with memory hierarchies
-
Li Y., Wolf W. Hardware/software co-synthesis with memory hierarchies. IEEE Transactions on CAD/ICAS October 1999, 18(10):1405-1417.
-
(1999)
IEEE Transactions on CAD/ICAS
, vol.18
, Issue.10
, pp. 1405-1417
-
-
Li, Y.1
Wolf, W.2
-
427
-
-
84882832170
-
-
LSI Logic Corporation Milpitas, CA, CW33000 MIPS Embedded Processor User's Manual, 1992.
-
LSI Logic Corporation Milpitas, CA, CW33000 MIPS Embedded Processor User's Manual, 1992.
-
-
-
-
428
-
-
0034996267
-
Processor-memory co-exploration driven by a memory-aware architecture description language
-
Mishra P., Grun P., Dutt N., Nicolau A. Processor-memory co-exploration driven by a memory-aware architecture description language. Proc. VLSI Design 2001.
-
(2001)
Proc. VLSI Design
-
-
Mishra, P.1
Grun, P.2
Dutt, N.3
Nicolau, A.4
-
430
-
-
0031099182
-
Synthesis of application-specific memory designs
-
Schmit H., Thomas D.E. Synthesis of application-specific memory designs. IEEE Transactions on VLSI Systems March 1997, 5(1):101-111.
-
(1997)
IEEE Transactions on VLSI Systems
, vol.5
, Issue.1
, pp. 101-111
-
-
Schmit, H.1
Thomas, D.E.2
-
432
-
-
0345855761
-
-
In Design Automation and Test in Europe, DATE, March
-
Cassidy, A. S., Paul, J. M., and Thomas, E. D. Layered. Multi-Threaded, High-Level Performance Design. In Design Automation and Test in Europe, DATE, pp. 954-959, March 2003.
-
(2003)
Layered. Multi-Threaded, High-Level Performance Design
, pp. 954-959
-
-
Cassidy, A.S.1
Paul, J.M.2
Thomas, E.D.3
-
433
-
-
0034589461
-
-
VHDL International User's Forum, October
-
Cesario, W., Gauthier, L., Lyonnard, D., Nicolescu, G., and Jerraya, A. An XML-based Meta-Model for the Design of Multiprocessor Embedded Systems. In VHDL International User's Forum, pp. 75-82, October 2000.
-
(2000)
An XML-based Meta-Model for the Design of Multiprocessor Embedded Systems
, pp. 75-82
-
-
Cesario, W.1
Gauthier, L.2
Lyonnard, D.3
Nicolescu, G.4
Jerraya, A.5
-
434
-
-
84893781814
-
-
Design Automation and Test in Europe, DATE, March
-
Gerstlauer, A., Yu, H., and Gajski, D. RTOS Modelling for System-Level Design. In Design Automation and Test in Europe, DATE, pp. 132-137, March 2003.
-
(2003)
RTOS Modelling for System-Level Design
, pp. 132-137
-
-
Gerstlauer, A.1
Yu, H.2
Gajski, D.3
-
435
-
-
84974687699
-
Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment
-
Liu C.W., Layland J.W. Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment. Journal of the ACM March 1973, 20(1):46-61.
-
(1973)
Journal of the ACM
, vol.20
, Issue.1
, pp. 46-61
-
-
Liu, C.W.1
Layland, J.W.2
-
436
-
-
84947245728
-
Modelling Real-Time Systems-Challenges and Work Directions
-
Sifakis J. Modelling Real-Time Systems-Challenges and Work Directions. EMSOFT, Lecture Notes in Computer Science 2211 October 2001, 373-389.
-
(2001)
EMSOFT, Lecture Notes in Computer Science 2211
, pp. 373-389
-
-
Sifakis, J.1
-
439
-
-
84870634342
-
Open SystemC Initiative (OSCI)
-
Open SystemC Initiative (OSCI) http://www.systemc.org.
-
-
-
-
442
-
-
1142307753
-
-
SASIMI, October
-
Tomiyama, H., Cao, Y., and Murakami, K. Modelling Fixed-Priority Preemptive Multi-Task Systems in SpecC. In SASIMI, pp. 93-100, October 2001.
-
(2001)
Modelling Fixed-Priority Preemptive Multi-Task Systems in SpecC
, pp. 93-100
-
-
Tomiyama, H.1
Cao, Y.2
Murakami, K.3
-
443
-
-
0004149896
-
-
Kluwer Academic Publishers, New York
-
Grotker T., Martin G., Liao S., Swan S. System Design with SystemC 2002, Kluwer Academic Publishers, New York.
-
(2002)
System Design with SystemC
-
-
Grotker, T.1
Martin, G.2
Liao, S.3
Swan, S.4
-
450
-
-
0025488794
-
Priority-Inheritance Protocols: An Approach to Real-Time Synchronization
-
Sha L., Rajkumar R., Lehoczky P.J. Priority-Inheritance Protocols: An Approach to Real-Time Synchronization. IEEE Transactions on Computers 1990, 39:1175-1185.
-
(1990)
IEEE Transactions on Computers
, vol.39
, pp. 1175-1185
-
-
Sha, L.1
Rajkumar, R.2
Lehoczky, P.J.3
-
451
-
-
0026118563
-
Stack-based Scheduling of Real-Time Processes
-
Baker T. Stack-based Scheduling of Real-Time Processes. Advances in Real-Time Systems March 1991, 3:64-96.
-
(1991)
Advances in Real-Time Systems
, vol.3
, pp. 64-96
-
-
Baker, T.1
-
455
-
-
21244496167
-
-
In Design Automation and Test in Europe, DATE, March
-
Schmitz, M., Al-Hashimi, B., and Eles, P. A. Co-Design Methodology for Energy-Efficient, Multi-Mode Embedded Systems with the consideration of Mode Execution Probabilities. In Design Automation and Test in Europe, DATE, pp. 960-965, March 2003.
-
(2003)
Co-Design Methodology for Energy-Efficient, Multi-Mode Embedded Systems with the consideration of Mode Execution Probabilities
, pp. 960-965
-
-
Schmitz, M.1
Al-Hashimi, B.2
Eles, P.A.3
-
457
-
-
0002927078
-
High Speed: Not the Only Way to Exploit the Intrinsic Computational Power of Silicon
-
Claasen T. High Speed: Not the Only Way to Exploit the Intrinsic Computational Power of Silicon. Proc Int Solid-State Circuits Conf. Feb. 1999, 22-25.
-
(1999)
Proc Int Solid-State Circuits Conf.
, pp. 22-25
-
-
Claasen, T.1
-
459
-
-
0002070785
-
Dynamic Memory Oriented Transformations in the MPEG4 IM1-player on a Low Power Platform
-
Marchal P., Wong C., Prayati A., Cossement N., Catthoor F., Lauwereins R., Verkest D., DeMan H. Dynamic Memory Oriented Transformations in the MPEG4 IM1-player on a Low Power Platform. Proc Intnl Wsh on Power Aware Computing Systems(PACS) Nov. 2000.
-
(2000)
Proc Intnl Wsh on Power Aware Computing Systems(PACS)
-
-
Marchal, P.1
Wong, C.2
Prayati, A.3
Cossement, N.4
Catthoor, F.5
Lauwereins, R.6
Verkest, D.7
DeMan, H.8
-
460
-
-
0035444245
-
Energy-aware Runtime Scheduling for Embedded Multiprocessor SoCs
-
Yang P., Wong C., Marchal P., Catthoor F., Desmet D., Verkest D., Lauwereins R. Energy-aware Runtime Scheduling for Embedded Multiprocessor SoCs. IEEE Design and Test of Computers Sept. 2001, 19(3).
-
(2001)
IEEE Design and Test of Computers
, vol.19
, Issue.3
-
-
Yang, P.1
Wong, C.2
Marchal, P.3
Catthoor, F.4
Desmet, D.5
Verkest, D.6
Lauwereins, R.7
-
461
-
-
0028320392
-
Scheduling Algorithms and Operation Systems Support for Real-Time Systems
-
1
-
Ramamritham K., Stankovic A.J. Scheduling Algorithms and Operation Systems Support for Real-Time Systems. Proceedings of the IEEE Jan. 1994, 82:55-67. 1.
-
(1994)
Proceedings of the IEEE
, vol.82
, pp. 55-67
-
-
Ramamritham, K.1
Stankovic, A.J.2
-
462
-
-
0029267687
-
Fixed Priority Preemptive Scheduling: An Historical Perspective
-
Audsley N., Burns A., Davis R., Tindell K., Wellings A. Fixed Priority Preemptive Scheduling: An Historical Perspective. Real-Time Systems 1995, 8(2):173-198.
-
(1995)
Real-Time Systems
, vol.8
, Issue.2
, pp. 173-198
-
-
Audsley, N.1
Burns, A.2
Davis, R.3
Tindell, K.4
Wellings, A.5
-
463
-
-
0025488794
-
Priority Inheritance Protocols: An Approach to Real-Time Synchronization
-
Sha L., Rajkumar R., Lehoczky P.J. Priority Inheritance Protocols: An Approach to Real-Time Synchronization. IEEE Transactions on Computers Sept. 1990, 39(9):1175-1185.
-
(1990)
IEEE Transactions on Computers
, vol.39
, Issue.9
, pp. 1175-1185
-
-
Sha, L.1
Rajkumar, R.2
Lehoczky, P.J.3
-
468
-
-
84974687699
-
Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment
-
Liu C.L., Layland W.J. Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment. Journal of the Association for Computing Machinery Jan. 1973, 20(1):46-61.
-
(1973)
Journal of the Association for Computing Machinery
, vol.20
, Issue.1
, pp. 46-61
-
-
Liu, C.L.1
Layland, W.J.2
-
469
-
-
0020271514
-
On the Complexity of Fixed-Priority Scheduling of Periodic Real-Time Tasks
-
Leung J.-T., Whitehead J. On the Complexity of Fixed-Priority Scheduling of Periodic Real-Time Tasks. Performance Evaluation 1982, 2:237-250.
-
(1982)
Performance Evaluation
, vol.2
, pp. 237-250
-
-
Leung, J.-T.1
Whitehead, J.2
-
470
-
-
0001552016
-
Dynamic Scheduling of Real-Time Tasks Under Precedence Constraints
-
Chetto H., Silly M., Bouchentouf T. Dynamic Scheduling of Real-Time Tasks Under Precedence Constraints. Real-Time Systems Sept. 1990, 2(3):181-194.
-
(1990)
Real-Time Systems
, vol.2
, Issue.3
, pp. 181-194
-
-
Chetto, H.1
Silly, M.2
Bouchentouf, T.3
-
472
-
-
0030109034
-
Scheduling Aperiodic Tasks in Dynamic Priority Systems
-
Spuri M., Buttazzo C.G. Scheduling Aperiodic Tasks in Dynamic Priority Systems. Real-Time Systems 1996, 10(2):179-210.
-
(1996)
Real-Time Systems
, vol.10
, Issue.2
, pp. 179-210
-
-
Spuri, M.1
Buttazzo, C.G.2
-
473
-
-
0026118563
-
Stack-Based Scheduling of Realtime Processes
-
Baker P.T. Stack-Based Scheduling of Realtime Processes. Real-Time Systems 1991, 3(1):67-99.
-
(1991)
Real-Time Systems
, vol.3
, Issue.1
, pp. 67-99
-
-
Baker, P.T.1
-
474
-
-
0029520321
-
Task Scheduling in Multiprocessing Systems
-
El-Rewini H., Ali H.H., Lewis T. Task Scheduling in Multiprocessing Systems. IEEE Computer Dec. 1995, 28(12):27-37.
-
(1995)
IEEE Computer
, vol.28
, Issue.12
, pp. 27-37
-
-
El-Rewini, H.1
Ali, H.H.2
Lewis, T.3
-
475
-
-
0027607336
-
Scheduling of DSP Programs onto Multiprocessors for Maximum Throughput
-
Hoang P.D., Rabaey M.J. Scheduling of DSP Programs onto Multiprocessors for Maximum Throughput. IEEE Transactions on Signal Processing June 1993, 41(6):2225-2235.
-
(1993)
IEEE Transactions on Signal Processing
, vol.41
, Issue.6
, pp. 2225-2235
-
-
Hoang, P.D.1
Rabaey, M.J.2
-
483
-
-
84882824848
-
-
http://www.crusoe.com/crusoe/index.html.
-
-
-
-
484
-
-
0034854528
-
Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors
-
Quan G., Hu X. Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors. Proceedings of the 38th Design Automation Conference 2001.
-
(2001)
Proceedings of the 38th Design Automation Conference
-
-
Quan, G.1
Hu, X.2
-
485
-
-
0034315851
-
A Dynamic Voltage Scaled Microprocessor System
-
Burd T.D., Pering T.A., Stratakos A.J., Brodersen W.R. A Dynamic Voltage Scaled Microprocessor System. IEEE J Solid-State Circuits Nov. 2000, 35(11):1571-1580.
-
(2000)
IEEE J Solid-State Circuits
, vol.35
, Issue.11
, pp. 1571-1580
-
-
Burd, T.D.1
Pering, T.A.2
Stratakos, A.J.3
Brodersen, W.R.4
-
486
-
-
0031624030
-
Power Optimization of Variable Voltage Core-Based Systems
-
Hong I., Kirovski D., Qu G., Potkonjak M., Srivastava B.M. Power Optimization of Variable Voltage Core-Based Systems. Proceedings of the 35th Design Automation Conference 1998, 176-181.
-
(1998)
Proceedings of the 35th Design Automation Conference
, pp. 176-181
-
-
Hong, I.1
Kirovski, D.2
Qu, G.3
Potkonjak, M.4
Srivastava, B.M.5
-
487
-
-
0034477891
-
Power-consious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-time Embedded Systems
-
Luo J., Jha N. Power-consious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-time Embedded Systems. IEEE/ACM International Conference on Computer-Aided Design Nov. 2000, 357-364.
-
(2000)
IEEE/ACM International Conference on Computer-Aided Design
, pp. 357-364
-
-
Luo, J.1
Jha, N.2
-
488
-
-
84962292024
-
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems
-
Luo J., Jha N. Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. 7th ASPDAC and 15th Int'l Conf on VLSI Design Jan. 2002, 719-726.
-
(2002)
7th ASPDAC and 15th Int'l Conf on VLSI Design
, pp. 719-726
-
-
Luo, J.1
Jha, N.2
-
491
-
-
0031373923
-
The Interaction of Architecture and Compilation Technology for High-performance Processor Design
-
Adve S., et al. The Interaction of Architecture and Compilation Technology for High-performance Processor Design. IEEE Computer Magazine Dec. 1997, 30(12):51-58.
-
(1997)
IEEE Computer Magazine
, vol.30
, Issue.12
, pp. 51-58
-
-
Adve, S.1
-
492
-
-
0003502725
-
-
Kluwer Academic Publishers, Boston
-
Catthoor F., Danckaert K., Kulkarni C., Brockmeyer E., Kjeldsberg P.G., Achteren T., Omnes T. Data Access and Storage Management for Embedded Programmable Processors 2002, Kluwer Academic Publishers, Boston.
-
(2002)
Data Access and Storage Management for Embedded Programmable Processors
-
-
Catthoor, F.1
Danckaert, K.2
Kulkarni, C.3
Brockmeyer, E.4
Kjeldsberg, P.G.5
Achteren, T.6
Omnes, T.7
-
493
-
-
77954563188
-
Task Concurrency Analysis and Exploration of Visual Texture Decoder on a Heterogeneous Platform
-
Ma Z., Wong C., Delfosse E., Vounckx J., Catthoor F., Himpe S., Deconinck G. Task Concurrency Analysis and Exploration of Visual Texture Decoder on a Heterogeneous Platform. IEEE Workshop on Signal Processing Systems (SIPS) 2003, 245-250.
-
(2003)
IEEE Workshop on Signal Processing Systems (SIPS)
, pp. 245-250
-
-
Ma, Z.1
Wong, C.2
Delfosse, E.3
Vounckx, J.4
Catthoor, F.5
Himpe, S.6
Deconinck, G.7
-
494
-
-
0347934778
-
Matador: an exploration environment for system-design
-
Marchal P., Jayapala M., Souza S.D., Yang P., Catthoor F., Deconinck G. Matador: an exploration environment for system-design. Journal of Circuits, Systems and Computers 2002, 11(5):503-535.
-
(2002)
Journal of Circuits, Systems and Computers
, vol.11
, Issue.5
, pp. 503-535
-
-
Marchal, P.1
Jayapala, M.2
Souza, S.D.3
Yang, P.4
Catthoor, F.5
Deconinck, G.6
-
495
-
-
4244175607
-
Energy Efficient System Design and Utilization
-
Dept. of Electrical Engineering, Stanford University
-
Simunic T. Energy Efficient System Design and Utilization. PhD thesis 2001, Dept. of Electrical Engineering, Stanford University.
-
(2001)
PhD thesis
-
-
Simunic, T.1
-
497
-
-
0003958368
-
-
Translated into English by Ann Schwier, S., (1971), Manual of Political Economy, MacMillan, London, Piccola Biblioteca Scientifica, Milan
-
Pareto V. Manuale di Economia Politica 1906, Translated into English by Ann Schwier, S., (1971), Manual of Political Economy, MacMillan, London, Piccola Biblioteca Scientifica, Milan.
-
(1906)
Manuale di Economia Politica
-
-
Pareto, V.1
-
498
-
-
84882831702
-
-
http://www.windriver.com/products/vspworks/index.html.
-
-
-
-
499
-
-
70350356025
-
-
ISSS+CODES, Newport Beach, CA
-
Yang, P., and Catthoor, F. Pareto-Optimization-Based Run-Time Task Scheduling for Embedded Systems. In ISSS+CODES, Newport Beach, CA, 2003.
-
(2003)
Pareto-Optimization-Based Run-Time Task Scheduling for Embedded Systems
-
-
Yang, P.1
Catthoor, F.2
-
501
-
-
84882905934
-
-
http://www.ilog.com/products/cplex/product/mip.cfm.
-
-
-
-
503
-
-
0003497543
-
Combining register allocation and instruction scheduling
-
Department of Computer Science, Stanford University
-
Motwani R., Palem K., Sarkar V., Reyen S. Combining register allocation and instruction scheduling. Technical Report STAN-CS-TN-95-22 1995, Department of Computer Science, Stanford University.
-
(1995)
Technical Report STAN-CS-TN-95-22
-
-
Motwani, R.1
Palem, K.2
Sarkar, V.3
Reyen, S.4
-
504
-
-
0141982145
-
Optimal and near-optimal solutions for hard compilation problems
-
Kremer U. Optimal and near-optimal solutions for hard compilation problems. Parallel Processing Letters 1997, 7(4).
-
(1997)
Parallel Processing Letters
, vol.7
, Issue.4
-
-
Kremer, U.1
-
505
-
-
0029719956
-
Software pipelining showdown: Optimal vheuristic, s., methods in a production compiler
-
Ruttenberg J., Gao G.R., Stoutchinin A., Lichtenstein W. Software pipelining showdown: Optimal vheuristic, s., methods in a production compiler. Proceedings of the ACM SIGPLAN '96 Conference on Programming Language Design and Implementation 1996, 1-11.
-
(1996)
Proceedings of the ACM SIGPLAN '96 Conference on Programming Language Design and Implementation
, pp. 1-11
-
-
Ruttenberg, J.1
Gao, G.R.2
Stoutchinin, A.3
Lichtenstein, W.4
-
506
-
-
0030211929
-
Optimal and near-optimal global register allocation using 0-1 integer programming
-
Goodwin D.W., Wilken K.D. Optimal and near-optimal global register allocation using 0-1 integer programming. Software-Practice & Experience August 1996, 26(8):929-965.
-
(1996)
Software-Practice & Experience
, vol.26
, Issue.8
, pp. 929-965
-
-
Goodwin, D.W.1
Wilken, K.D.2
-
508
-
-
0034819721
-
Optimal spilling for CISC machines with few registers
-
C. Norris, R. James, B. Fenwick (Eds.)
-
Appel A., George L. Optimal spilling for CISC machines with few registers. Proceedings of PLDI'01, ACM SIGPLAN Conference on Programming Language Design and Implementation 2001, 243-253. C. Norris, R. James, B. Fenwick (Eds.).
-
(2001)
Proceedings of PLDI'01, ACM SIGPLAN Conference on Programming Language Design and Implementation
, pp. 243-253
-
-
Appel, A.1
George, L.2
-
509
-
-
84947795503
-
An integer linear programming model of software pipelining for the MIPS R8000 processor
-
Springer-Verlag, PaCT'97, Parallel Computing Technologies, 4th International Conference
-
Stoutchinin A. An integer linear programming model of software pipelining for the MIPS R8000 processor. LNCS 1277 1997, 121-135. Springer-Verlag.
-
(1997)
LNCS 1277
, pp. 121-135
-
-
Stoutchinin, A.1
-
513
-
-
0034448098
-
Optimal instruction scheduling using integer programming
-
5
-
Wilken K.D., Liu J., Heffernan M. Optimal instruction scheduling using integer programming. Proceedings of PLDI'00, ACM SIGPLAN Conference on Programming Language Design and Implementation May 2000, 35:121-133. 5.
-
(2000)
Proceedings of PLDI'00, ACM SIGPLAN Conference on Programming Language Design and Implementation
, vol.35
, pp. 121-133
-
-
Wilken, K.D.1
Liu, J.2
Heffernan, M.3
-
514
-
-
0036974702
-
Energy-conscious compilation based on voltage scaling
-
Saputra H., Kandemir M., Vijaykrishnan N., Irwin M.J., Hu J., Hsu C.-H., Kremer U. Energy-conscious compilation based on voltage scaling. Proceedings of the 2002 Joint Conference on Languages, Compilers and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES/SCOPES'02) June 2002, 2-11.
-
(2002)
Proceedings of the 2002 Joint Conference on Languages, Compilers and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES/SCOPES'02)
, pp. 2-11
-
-
Saputra, H.1
Kandemir, M.2
Vijaykrishnan, N.3
Irwin, M.J.4
Hu, J.5
Hsu, C.-H.6
Kremer, U.7
-
515
-
-
0036974914
-
-
LCTES'02, Languages, Compilers and Tools for Embedded Systems joint with SCOPES'02, Software and Compilers for Embedded Systems, pp. 120-129, Berlin, Germany, June
-
Naik, M. and Palsberg, J. Compiling with code-size constraints. In LCTES'02, Languages, Compilers and Tools for Embedded Systems joint with SCOPES'02, Software and Compilers for Embedded Systems, pp. 120-129, Berlin, Germany, June 2002.
-
(2002)
Compiling with code-size constraints
-
-
Naik, M.1
Palsberg, J.2
-
517
-
-
0018105622
-
A theory of type polymorphism in programming
-
Milner R. A theory of type polymorphism in programming. Journal of Computer and System Sciences 1978, 17:348-375.
-
(1978)
Journal of Computer and System Sciences
, vol.17
, pp. 348-375
-
-
Milner, R.1
-
518
-
-
0347029094
-
Replacing function parameters by global variables
-
DIKU, University of Copenhagen
-
Sestoft P. Replacing function parameters by global variables. Master's thesis September 1989, DIKU, University of Copenhagen.
-
(1989)
Master's thesis
-
-
Sestoft, P.1
-
519
-
-
0008521377
-
Analysis and Efficient Implementation of Functional Programs
-
DIKU, University of Copenhagen
-
Sestoft P. Analysis and Efficient Implementation of Functional Programs. PhD thesis October 1991, DIKU, University of Copenhagen.
-
(1991)
PhD thesis
-
-
Sestoft, P.1
-
521
-
-
84882918901
-
Preliminary version in Proceedings of CAAP'94, Colloquium on Trees in Algebra and Programming
-
Edinburgh, Scotland, Springer-Verlag
-
Palsberg J. Preliminary version in Proceedings of CAAP'94, Colloquium on Trees in Algebra and Programming. LNCS 878 April 1994, 276-290. Edinburgh, Scotland, Springer-Verlag.
-
(1994)
LNCS 878
, pp. 276-290
-
-
Palsberg, J.1
-
522
-
-
84957104053
-
A modular, extensible proof method for small-step flow analyses
-
Springer-Verlag, M. Daniel Le (Ed.) Proceedings of ESOP 2002, 11th European symposium on Programming, held as Part of the Joint European Conference on Theory and Practice of Software, ETAPS 2002
-
Wand M., Williamson G.B. A modular, extensible proof method for small-step flow analyses. LNCS 2305 2002, 213-227. Springer-Verlag. M. Daniel Le (Ed.).
-
(2002)
LNCS 2305
, pp. 213-227
-
-
Wand, M.1
Williamson, G.B.2
-
523
-
-
85033665033
-
The typed lambda-calculus with first-class processes
-
F.Nielson The typed lambda-calculus with first-class processes. Proceedings of PARLE April 1989, 357-373.
-
(1989)
Proceedings of PARLE
, pp. 357-373
-
-
Nielson, F.1
-
527
-
-
85035102569
-
Continuation semantics in typed lambda-calculi
-
Springer-Verlag, Proceedings of Logics of Programs
-
Meyer A.R., Wand M. Continuation semantics in typed lambda-calculi. LNCS 193 1985, 219-224. Springer-Verlag.
-
(1985)
LNCS 193
, pp. 219-224
-
-
Meyer, A.R.1
Wand, M.2
-
530
-
-
17144396747
-
TIL: A type directed optimizing compiler for MIn, L.
-
ACM Press
-
Tarditi D., Morrisett G., Cheng P., Stone C., Harper R., Lee P TIL: A type directed optimizing compiler for MIn, L. ACM SIGPLAN Conference on Programming Language Design and Implementation 1996, 181-192. ACM Press.
-
(1996)
ACM SIGPLAN Conference on Programming Language Design and Implementation
, pp. 181-192
-
-
Tarditi, D.1
Morrisett, G.2
Cheng, P.3
Stone, C.4
Harper, R.5
Lee, P.6
-
531
-
-
0031679751
-
From system F to typed assembly language
-
Morrisett G., Walker D., Crary K., Glew N. From system F to typed assembly language. Proceedings of POPL'98, 25th Annual SIGPLAN-SIGACT Symposium on Principles of Programming Languages 1998, 85-97.
-
(1998)
Proceedings of POPL'98, 25th Annual SIGPLAN-SIGACT Symposium on Principles of Programming Languages
, pp. 85-97
-
-
Morrisett, G.1
Walker, D.2
Crary, K.3
Glew, N.4
-
532
-
-
0001053840
-
Separate abstract interpretation for control-flow analysis
-
Springer-Verlag, Proceedings of TACS'94, Theoretical Aspects of Computing Software
-
Tang Y.M., Jouvelot P. Separate abstract interpretation for control-flow analysis. LNCS 789 1994, 224-243. Springer-Verlag.
-
(1994)
LNCS 789
, pp. 224-243
-
-
Tang, Y.M.1
Jouvelot, P.2
-
533
-
-
84955607179
-
Control-flow analysis and type systems
-
Springer-Verlag, Glasgow, Scotland, Proceedings of SAS'95, International Static Analysis Symposium
-
N.Heintze Control-flow analysis and type systems. LNCS 983 September 1995, 189-206. Springer-Verlag, Glasgow, Scotland.
-
(1995)
LNCS 983
, pp. 189-206
-
-
Heintze, N.1
-
534
-
-
84956969336
-
A typed intermediate language for flow-directed compilation
-
Springer-Verlag, In Proceedings of TAPSOFT'97, Theory and Practice of Software Development
-
Wells J.B., Allyn Dimock, Robert Muller, Franklyn Turbak A typed intermediate language for flow-directed compilation. LNCS 1214 1997, Springer-Verlag.
-
(1997)
LNCS 1214
-
-
Wells, J.B.1
Allyn, D.2
Robert, M.3
Franklyn, T.4
-
539
-
-
0035609108
-
From polyvariant flow information to intersection and union types
-
Palsberg J., Pavlopoulou C. From polyvariant flow information to intersection and union types. Journal of Functional Programming May 2001, 11(3):263-317.
-
(2001)
Journal of Functional Programming
, vol.11
, Issue.3
, pp. 263-317
-
-
Palsberg, J.1
Pavlopoulou, C.2
-
543
-
-
84882863402
-
-
ITRS available at
-
ITRS available at. http://public.itrs.net.
-
-
-
-
544
-
-
84882914113
-
-
A. 2. 7V 11. 8mW Baseband ADC with 72dB Dynamic Range for GSM Applications
-
Nagari A., et al. 21st Custom Integrated Circuits Conference 1999, A. 2. 7V 11. 8mW Baseband ADC with 72dB Dynamic Range for GSM Applications.
-
(1999)
21st Custom Integrated Circuits Conference
-
-
Nagari, A.1
-
545
-
-
84882826883
-
-
http://www.semiconductor.philips.com/platforms/nexperia.
-
-
-
-
546
-
-
0033341604
-
Designing and Programming the Emotion Engine
-
Oka M., Suzuoki M. Designing and Programming the Emotion Engine. IEEE Micro Nov/Dec 1999, vol. 19:6:20-28.
-
(1999)
IEEE Micro
, pp. 20-28
-
-
Oka, M.1
Suzuoki, M.2
-
547
-
-
0005458446
-
Network Processors: A Perspective on Market Requirements
-
Paulin P., Karim F., Bromley P. Network Processors: A Perspective on Market Requirements. Proc. of DATE 2001.
-
(2001)
Proc. of DATE
-
-
Paulin, P.1
Karim, F.2
Bromley, P.3
-
551
-
-
85008048480
-
Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software
-
Gauthier L., Yoo S., Jerraya A.A. Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software. IEEE TCAD November 2001, Vol. 20 N11, r.
-
(2001)
IEEE TCAD
-
-
Gauthier, L.1
Yoo, S.2
Jerraya, A.A.3
-
552
-
-
84908619102
-
-
Keutzer K. A Disciplined Approach to the Development of Platform Architectures, Synthesis and System Integration of Mixed Technologies (SASIMI), Nara, Japan, October 18-19, 2001.
-
(2001)
A Disciplined Approach to the Development of Platform Architectures, Synthesis and System Integration of Mixed Technologies (SASIMI), Nara, Japan,
-
-
Keutzer, K.1
-
553
-
-
0030145171
-
The COSYMA environment for hardware/software cosynthesis of small embedded systems
-
Ernst R., et al. The COSYMA environment for hardware/software cosynthesis of small embedded systems. Microprocessors and Microsystems 1996.
-
(1996)
Microprocessors and Microsystems
-
-
Ernst, R.1
-
554
-
-
0003733188
-
Hardware-Software Co-design of Embedded Systems
-
Kluwer Academic Press
-
Balarin F., et al. Hardware-Software Co-design of Embedded Systems. The POLIS approach 1997, Kluwer Academic Press.
-
(1997)
The POLIS approach
-
-
Balarin, F.1
-
557
-
-
0034428118
-
System-level design: orthogonalization of concerns and platform-based design
-
Keutzer K., et al. System-level design: orthogonalization of concerns and platform-based design. IEEE TCAD Dec. 2000.
-
(2000)
IEEE TCAD
-
-
Keutzer, K.1
-
559
-
-
0036859776
-
Multiprocessor SoC platforms: A Component-Based Design Approach
-
Cesário W.O., et al. Multiprocessor SoC platforms: A Component-Based Design Approach. IEEE Design & Test of Computers Nov.-Dec., 2002, Vol. 19(Issue: 6).
-
(2002)
IEEE Design & Test of Computers
, vol.19
, Issue.ISSUE 6
-
-
Cesário, W.O.1
-
560
-
-
0034846659
-
Addressing the System-on-Chip Interconnect Woes Through Communication-Based Design
-
Sgroi M., et al. Addressing the System-on-Chip Interconnect Woes Through Communication-Based Design. Proc. of 38th Design Automation Conference June 2001.
-
(2001)
Proc. of 38th Design Automation Conference
-
-
Sgroi, M.1
-
561
-
-
84882841434
-
-
IBM Inc.
-
IBM Inc. Blue Logic Technology http://www.chips.ibm.com/bluelogic.
-
Blue Logic Technology
-
-
-
562
-
-
84882860461
-
-
Virstual Stocket Interface Alliance
-
Virstual Stocket Interface Alliance http://www.vsi.org.
-
-
-
-
563
-
-
0003350995
-
PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia
-
Leijten J.A.J., et al. PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. Proc. of ICCD 1997.
-
(1997)
Proc. of ICCD
-
-
Leijten, J.A.J.1
-
564
-
-
84882897872
-
-
N2C
-
CoWare Inc. N2C. http://www.coware.com.
-
-
-
CoWare, Inc.1
-
565
-
-
0034841440
-
MicroNetwork-Based Integration for SOCs
-
Wingard D. MicroNetwork-Based Integration for SOCs. Proc. of DAC June 2001.
-
(2001)
Proc. of DAC
-
-
Wingard, D.1
-
566
-
-
0032630848
-
Methodology and technology for virtual component driven hardware/software co-design on the system-level
-
Krolikoski S.J., Schirrmeister F., Salefski B., Rowson J., Martin G. Methodology and technology for virtual component driven hardware/software co-design on the system-level. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems (ISCAS) May-June, 1999, 456-459.
-
(1999)
Proceedings of the 1999 IEEE International Symposium on Circuits and Systems (ISCAS)
, pp. 456-459
-
-
Krolikoski, S.J.1
Schirrmeister, F.2
Salefski, B.3
Rowson, J.4
Martin, G.5
-
567
-
-
84882928582
-
-
http://www.synopsys.com.
-
-
-
-
570
-
-
4243681494
-
ProGram: A Grammar-Based Method for Specification and Hardware Synthesis of Communication Protocols
-
Department of Electronics, Electronics System Design, Royall Institute of Technology, Kista, Sweden
-
Oberg J. ProGram: A Grammar-Based Method for Specification and Hardware Synthesis of Communication Protocols. PhD thesis 7 May 1999, Department of Electronics, Electronics System Design, Royall Institute of Technology, Kista, Sweden.
-
(1999)
PhD thesis
-
-
Oberg, J.1
-
573
-
-
0029720741
-
Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications
-
Vercauteren S., Lin B., Man H.D. Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications. Proceedings of DAC June 1996.
-
(1996)
Proceedings of DAC
-
-
Vercauteren, S.1
Lin, B.2
Man, H.D.3
-
575
-
-
84882816477
-
-
OSCI
-
OSCI. http://www.systemc.org.
-
-
-
-
576
-
-
0043198742
-
High-level Architectural Co-Simulation Using Esterel and C
-
Chatelain A., Placido G., LaRosa A., Mathys Y., Lavagno L. High-level Architectural Co-Simulation Using Esterel and C. CODES01, Copenhagen 2001.
-
(2001)
CODES01, Copenhagen
-
-
Chatelain, A.1
Placido, G.2
LaRosa, A.3
Mathys, Y.4
Lavagno, L.5
-
577
-
-
0035444356
-
Colif: A design representation for application-specific multiprocessor SOCs
-
Cesário W.O., et al. Colif: A design representation for application-specific multiprocessor SOCs. IEEE Design & Test of Computers Sept.-Oct. 2001, Vol. 18(Issue 5):8-20.
-
(2001)
IEEE Design & Test of Computers
, vol.18
, Issue.ISSUE 5
, pp. 8-20
-
-
Cesário, W.O.1
-
578
-
-
0034854046
-
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip
-
Las Vegas
-
Lyonnard D., Yoo S., Baghdadi A., Jerraya A.A. Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. Proc. of DAC 2001, Las Vegas.
-
(2001)
Proc. of DAC
-
-
Lyonnard, D.1
Yoo, S.2
Baghdadi, A.3
Jerraya, A.A.4
-
580
-
-
0005419903
-
The Zipper prototype: A Complete and Flexible VDSL Multi-carrier Solution
-
Diaz-Nava M., Okvist G.S. The Zipper prototype: A Complete and Flexible VDSL Multi-carrier Solution. ST Journal special issue xDSL September 2001.
-
(2001)
ST Journal special issue xDSL
-
-
Diaz-Nava, M.1
Okvist, G.S.2
-
581
-
-
0033297666
-
TriMedia CPU64 Architecture
-
van Eijndhoven J.T.J., Sijstermans F.W., Vissers K.A., Pol E.J.D., Tromp M.J.A., Struik P., Bloks R.H.J., van der Wolf P., Pimentel A.D., Vranken H.P.E. TriMedia CPU64 Architecture. Proceedings of the 1999 International Conference on Computer Design October 1999, 586-592. http://www.semiconductors.philips.com/trimedia.
-
(1999)
Proceedings of the 1999 International Conference on Computer Design
, pp. 586-592
-
-
van Eijndhoven, J.T.J.1
Sijstermans, F.W.2
Vissers, K.A.3
Pol, E.J.D.4
Tromp, M.J.A.5
Struik, P.6
Bloks, R.H.J.7
van der Wolf, P.8
Pimentel, A.D.9
Vranken, H.P.E.10
-
582
-
-
0002909633
-
Motion compensated interframe coding for videoconferencing
-
Koga T., Iinuma I., Hirano A., Ijima Y., Ishiguro T. Motion compensated interframe coding for videoconferencing. Proceedings, National Communications Conference 1981, 531-535.
-
(1981)
Proceedings, National Communications Conference
, pp. 531-535
-
-
Koga, T.1
Iinuma, I.2
Hirano, A.3
Ijima, Y.4
Ishiguro, T.5
-
584
-
-
0032138862
-
A novel unrestricted center-biased diamond search algorithm for block motion estimation
-
Tham J.Y., Ranganath S., Ranganath M., Kassim A.A. A novel unrestricted center-biased diamond search algorithm for block motion estimation. IEEE Transactions on Circuits and Systems for Video Technology August 1998, 8(4):369-377.
-
(1998)
IEEE Transactions on Circuits and Systems for Video Technology
, vol.8
, Issue.4
, pp. 369-377
-
-
Tham, J.Y.1
Ranganath, S.2
Ranganath, M.3
Kassim, A.A.4
-
586
-
-
0022118981
-
Motion compensated predictive interframe coding
-
Kappagantula S., Rao K.R. Motion compensated predictive interframe coding. IEEE Transactions on Communication September 1985, 33(9):1011-1015.
-
(1985)
IEEE Transactions on Communication
, vol.33
, Issue.9
, pp. 1011-1015
-
-
Kappagantula, S.1
Rao, K.R.2
-
587
-
-
0036715137
-
Smart cameras as embedded systems
-
Wolf W., Ozer B., Lv T. Smart cameras as embedded systems. IEEE Computer September 2002, 35(9):48-53.
-
(2002)
IEEE Computer
, vol.35
, Issue.9
, pp. 48-53
-
-
Wolf, W.1
Ozer, B.2
Lv, T.3
-
589
-
-
0004279995
-
Multimedia architectures: from desktop systems to portable appliances
-
SPIE
-
Bhaskaran V., et al. Multimedia architectures: from desktop systems to portable appliances. Proceedings of Multimedia Hardware Architectures February 1997, vol. 3021. SPIE.
-
(1997)
Proceedings of Multimedia Hardware Architectures
, vol.3021
-
-
Bhaskaran, V.1
-
590
-
-
0027206012
-
HP's PA7100LC: A low-cost superscaler PA-RISC processor
-
Knebel P., et al. HP's PA7100LC: A low-cost superscaler PA-RISC processor. COMPCON 1993.
-
(1993)
COMPCON
-
-
Knebel, P.1
-
591
-
-
84882827468
-
UltraSPARC: the next generation superscaler 64-bit SPARC
-
Greenley D., et al. UltraSPARC: the next generation superscaler 64-bit SPARC. COMPCON 1995.
-
(1995)
COMPCON
-
-
Greenley, D.1
-
592
-
-
0030826020
-
Intel MMX for Multimedia PCs
-
Peleg A., et al. Intel MMX for Multimedia PCs. Communications of the ACM January 1997, 40(1).
-
(1997)
Communications of the ACM
, vol.40
, Issue.1
-
-
Peleg, A.1
-
593
-
-
84882829448
-
MMX(tm) Technology Architecture Overview
-
Available at
-
MMX(tm) Technology Architecture Overview Available at. http://www.intel.com/technology/itj/q31997/articles/art_2.htm.
-
-
-
-
594
-
-
84882911282
-
-
Pentium Manuals, Available at
-
Pentium Manuals Available at. http://x86.ddj.com/intel.doc/586manuals.htm.
-
-
-
-
595
-
-
84882846148
-
Cyrix 233 MHz MediaGX(tm)
-
Available at
-
Cyrix 233 MHz MediaGX(tm) Available at. http://bwrc.eecs.berkeley.edu/CIC/announce/1998/MediaGX-233.html.
-
-
-
-
596
-
-
84882856179
-
Mobile AMD-K6 Processor
-
Available at
-
Mobile AMD-K6 Processor Available at. http://www.baznet.freeserve.co.uk/AMD-K6.htm.
-
-
-
-
597
-
-
84882878493
-
Hardware/Software Interactions on the Mpact Media Processor
-
Available at
-
Hardware/Software Interactions on the Mpact Media Processor Available at. http://www.hotchips.org/archive/hc8/hc8pres_pdf/6.2.pdf.
-
-
-
-
598
-
-
0029777661
-
An Architectural Overview of the Programmable Multimedia Processor, TM-1
-
Rathnam S., Slavenburg G. An Architectural Overview of the Programmable Multimedia Processor, TM-1. COMPCON 1996.
-
(1996)
COMPCON
-
-
Rathnam, S.1
Slavenburg, G.2
-
599
-
-
84882850412
-
-
Philips Media Processor, Available at
-
Philips Media Processor Available at. http://www.semiconductors.philips.com/platforms/nexperia/media_processin g/products/media_proc_ic/index.html.
-
-
-
-
601
-
-
84882899663
-
-
Real World Signal Processing, Available at
-
Real World Signal Processing Available at. http://dspvillage.tcom,i.,/docs/allproductree.jhtml.
-
-
-
-
603
-
-
0026942592
-
A Single-Chip Multiprocessor for Multimedia: The MVP
-
Guttag K., et al. A Single-Chip Multiprocessor for Multimedia: The MVP. IEEE Computer Graphics & Applications November 1992.
-
(1992)
IEEE Computer Graphics & Applications
-
-
Guttag, K.1
-
604
-
-
0041606016
-
VIS Speeds New Media Processing
-
Tremblay M., et al. VIS Speeds New Media Processing. IEEE Micro August 1996.
-
(1996)
IEEE Micro
-
-
Tremblay, M.1
-
605
-
-
84882920607
-
-
The Silicon Graphics Power Challenge
-
The Silicon Graphics Power Challenge Available at. http://www.top500.org./ORSC/1996/node23.html.
-
-
-
-
606
-
-
0035444259
-
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
-
Dutta S., et al. Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems. IEEE Design and Test of Computers September/October 2001.
-
(2001)
IEEE Design and Test of Computers
-
-
Dutta, S.1
-
610
-
-
84882854781
-
-
Available at
-
Tensilica Available at. http://www.tensilica.com/.
-
Tensilica
-
-
-
611
-
-
84882906600
-
-
ARC Available at
-
ARC Available at. http://www.arc.com/.
-
-
-
-
614
-
-
84882856628
-
Reconfigurable architectures for video processing: Gries, M.
-
12, Available at, Technical University of Hamburg-Harburg, Germany
-
Reconfigurable architectures for video processing: Gries, M. MS thesis 12/1996, Available at, Technical University of Hamburg-Harburg, Germany. http://www-cad.eecs.berkeley.edu/~gries/abstracts/diplom.html.
-
(1996)
MS thesis
-
-
-
615
-
-
84882810911
-
-
Available at
-
Defining platform-based design Available at. http://www.eedesign.com/features/exclusive/OEG20020204S0062.
-
Defining platform-based design
-
-
-
616
-
-
0041347877
-
System on a Chip: Changing IC Design Today and in the Future
-
Claasen T. System on a Chip: Changing IC Design Today and in the Future. IEEE Micro May/June 2003.
-
(2003)
IEEE Micro
-
-
Claasen, T.1
-
617
-
-
84882883321
-
SOC Design Methodologies
-
Kluwer Academic Publishers, Norwell, MA
-
Chang H. SOC Design Methodologies. Winning the SOC Revolution 2003, Kluwer Academic Publishers, Norwell, MA.
-
(2003)
Winning the SOC Revolution
-
-
Chang, H.1
-
619
-
-
84882861852
-
-
CoreConnect Bus Architecture
-
CoreConnect Bus Architecture Available at. http://www.chips.ibm.com/products/core-connect.
-
-
-
-
620
-
-
3042640630
-
A Comparison of Five Different Multiprocessor SoC Bus Architectures
-
Rye K.K., et al. A Comparison of Five Different Multiprocessor SoC Bus Architectures. Euromicro Symposium on Digital Systems Design September, 2001.
-
(2001)
Euromicro Symposium on Digital Systems Design
-
-
Rye, K.K.1
-
622
-
-
84882841974
-
-
IEEE P1500 Standard for Embedded Core Test (SECT), Available at
-
IEEE P1500 Standard for Embedded Core Test (SECT) Available at. http://grouper.ieee.org/groups/1500.
-
-
-
-
623
-
-
0033316969
-
Towards a Standard for Embedded Core Test: An Example
-
Marinissen E., et al. Towards a Standard for Embedded Core Test: An Example. IEEE International Test Conference September 1999.
-
(1999)
IEEE International Test Conference
-
-
Marinissen, E.1
-
624
-
-
84882882911
-
Architecture and Compiler Design Issues in Programmable Media Processors
-
Princeton University
-
Jason Fritts Architecture and Compiler Design Issues in Programmable Media Processors. Ph. D. dissertation January 2000, Princeton University.
-
(2000)
Ph. D. dissertation
-
-
Jason, F.1
-
632
-
-
84882917906
-
Curriculum 68, A Report of the ACM Curriculum Committee on Computer Science
-
Curriculum 68, A Report of the ACM Curriculum Committee on Computer Science. Communications of the ACM 1968, Vol. 11(No. 3).
-
(1968)
Communications of the ACM
, vol.11
, Issue.3
-
-
-
633
-
-
0001839355
-
Fundamentals of a theory of asynchronous information flow
-
Petri C. Fundamentals of a theory of asynchronous information flow. Proc. IFIP Congress 1962, 62:386-390.
-
(1962)
Proc. IFIP Congress
, vol.62
, pp. 386-390
-
-
Petri, C.1
-
634
-
-
0018005391
-
Communicating Sequential Processes
-
Hoare C.A.R. Communicating Sequential Processes. Communications of the ACM Aug. 1978, Vol. 21(No. 8).
-
(1978)
Communications of the ACM
, vol.21
, Issue.8
-
-
Hoare, C.A.R.1
-
636
-
-
0000087207
-
The semantics of a simple language for parallel programming
-
North-Holland, Amsterdam, The Netherlands
-
Kahn G. The semantics of a simple language for parallel programming. Proceedings of the IFIP Congress 74 1974, North-Holland, Amsterdam, The Netherlands.
-
(1974)
Proceedings of the IFIP Congress 74
-
-
Kahn, G.1
-
637
-
-
0023365727
-
Statecharts: A visual formalism for complex systems
-
Harel D. Statecharts: A visual formalism for complex systems. Science of Computer Programming 1987, 231-274.
-
(1987)
Science of Computer Programming
, pp. 231-274
-
-
Harel, D.1
-
638
-
-
0002700584
-
On describing behavior and implementation of distributed systems
-
Lynch N., Fischer J. On describing behavior and implementation of distributed systems. Theoretical Computer Science 1981, 13(1).
-
(1981)
Theoretical Computer Science
, vol.13
, Issue.1
-
-
Lynch, N.1
Fischer, J.2
-
641
-
-
0003547470
-
-
Addison-Wesley, Reading, MA
-
Booch G., Rumbaugh J., Jacobson I. The Unified Modeling Language User Guide 1999, Addison-Wesley, Reading, MA.
-
(1999)
The Unified Modeling Language User Guide
-
-
Booch, G.1
Rumbaugh, J.2
Jacobson, I.3
-
643
-
-
0026220148
-
The synchronous approach to reactive and real-time systems
-
Benveniste A., Berry G. The synchronous approach to reactive and real-time systems. Proceedings of the IEEE Sept. 1991, 1270-1282.
-
(1991)
Proceedings of the IEEE
, pp. 1270-1282
-
-
Benveniste, A.1
Berry, G.2
-
646
-
-
0025416878
-
STATEMATE: a working environment for the development of complex reactive systems
-
Harel D., Lachover H., Naamad A., Pnueli A., Politi M., Sherman R., Shtul-Trauring A., Trakhtenbrot M. STATEMATE: a working environment for the development of complex reactive systems. IEEE Trans Software Engineering April 1990, 403-414.
-
(1990)
IEEE Trans Software Engineering
, pp. 403-414
-
-
Harel, D.1
Lachover, H.2
Naamad, A.3
Pnueli, A.4
Politi, M.5
Sherman, R.6
Shtul-Trauring, A.7
Trakhtenbrot, M.8
-
649
-
-
0001951703
-
System Timing
-
C. Mead, Conway, L., Addison-Wesley, Reading, MA
-
Seitz L.C. System Timing. Introduction to VLSI Systems 1980, C. Mead, Conway, L., Addison-Wesley, Reading, MA.
-
(1980)
Introduction to VLSI Systems
-
-
Seitz, L.C.1
-
651
-
-
0242444222
-
Taming Heterogeneity-the Ptolemy Approach
-
Eker J., Janneck J., Lee E., Liu J., Liu X., Ludvig J., Neuendorfer S., Sachs S., Xiong Y. Taming Heterogeneity-the Ptolemy Approach. Proceedings of the IEEE January 2003, 127-144.
-
(2003)
Proceedings of the IEEE
, pp. 127-144
-
-
Eker, J.1
Janneck, J.2
Lee, E.3
Liu, J.4
Liu, X.5
Ludvig, J.6
Neuendorfer, S.7
Sachs, S.8
Xiong, Y.9
-
652
-
-
0002152274
-
Turning Clockwise: Using UML in the Real-Time Domain
-
Selic B. Turning Clockwise: Using UML in the Real-Time Domain. Comm of the ACM Oct. 1999, 46-54.
-
(1999)
Comm of the ACM
, pp. 46-54
-
-
Selic, B.1
-
653
-
-
0034428118
-
System-level design: orthogonalisation of concerns and platform-based design
-
Keutzer K., Malik A., Newton A.R., Rabaey J., Sangiovanni-Vincentelli A. System-level design: orthogonalisation of concerns and platform-based design. IEEE Transactions on CAD December 2000, 1523-1543.
-
(2000)
IEEE Transactions on CAD
, pp. 1523-1543
-
-
Keutzer, K.1
Malik, A.2
Newton, A.R.3
Rabaey, J.4
Sangiovanni-Vincentelli, A.5
-
654
-
-
84882864640
-
-
DAC
-
Paul J., Bobrek A., Nelson J., Pieper J., Thomas D. Schedulers as Model-Based Design Elements in Programmable Heterogeneous Multiprocessors June, 2003, DAC.
-
(2003)
Schedulers as Model-Based Design Elements in Programmable Heterogeneous Multiprocessors
-
-
Paul, J.1
Bobrek, A.2
Nelson, J.3
Pieper, J.4
Thomas, D.5
-
656
-
-
84882856506
-
-
Layered, Multi-Threaded, High-Level Performance Design. DATE
-
Cassidy, A., Paul, J., and Thomas, D. Layered, Multi-Threaded, High-Level Performance Design. DATE 2003.
-
(2003)
-
-
Cassidy, A.1
Paul, J.2
Thomas, D.3
-
657
-
-
84882887769
-
-
A layered, codesign virtual machine approach to modeling computer systems, DATE
-
Paul, J., and Thomas, D. A layered, codesign virtual machine approach to modeling computer systems, DATE 2002.
-
(2002)
-
-
Paul, J.1
Thomas, D.2
-
658
-
-
84882821489
-
-
http://www.ece.cmu.edu.
-
-
-
-
660
-
-
85008521306
-
Are Single-Chip Multiprocessors in Reach?
-
Are Single-Chip Multiprocessors in Reach?. IEEE Design & Test Jan-Feb 2001.
-
(2001)
IEEE Design & Test
-
-
-
661
-
-
0036149420
-
-
Networks on chips: A New SoC Paradigm, Computer, J02, a
-
Benini, L., and De Micheli, G. Networks on chips: A New SoC Paradigm, Computer, J02, a, pp. 70-78.
-
-
-
Benini, L.1
De Micheli, G.2
-
665
-
-
0003733188
-
-
Kluwer Academic Publishers, Boston: Dordrecht
-
Balarin F., Chiodo M., Giusto P., Hsieh H., Jurecska A., Lavagno L., Passerone C., Sangovanni-Vincentelli A., Sentovich E., Suzuki K., Tabbara B. Hardware-software co-design of embedded systems: the Polis approach 1997, Kluwer Academic Publishers, Boston: Dordrecht.
-
(1997)
Hardware-software co-design of embedded systems: the Polis approach
-
-
Balarin, F.1
Chiodo, M.2
Giusto, P.3
Hsieh, H.4
Jurecska, A.5
Lavagno, L.6
Passerone, C.7
Sangovanni-Vincentelli, A.8
Sentovich, E.9
Suzuki, K.10
Tabbara, B.11
-
666
-
-
0003346051
-
Ptolemy: a framework for simulating and prototyping heterogeneous systems
-
special issue on Simulation Software Development
-
Buck J., Ha S., Lee E.A., Messerschmitt G.D. Ptolemy: a framework for simulating and prototyping heterogeneous systems. International Journal of Computer Simulation January 1990, special issue on Simulation Software Development.
-
(1990)
International Journal of Computer Simulation
-
-
Buck, J.1
Ha, S.2
Lee, E.A.3
Messerschmitt, G.D.4
-
667
-
-
0004149896
-
-
Kluwer Academic Publishers, Boston: Dordrecht
-
Grotker T., Martin G., Liao S., Swan S. System design with SystemC 2002, Kluwer Academic Publishers, Boston: Dordrecht.
-
(2002)
System design with SystemC
-
-
Grotker, T.1
Martin, G.2
Liao, S.3
Swan, S.4
-
669
-
-
0036047772
-
Component-based design approach for multicore SoCs
-
Cesario W., Baghdadi A., Gauthier L., Lyonnard D., Nicolescu G., Paviot Y., Yoo S., Jerraya A.A., Diaz-Nava M. Component-based design approach for multicore SoCs. Proceedings of the 39th ACM/IEEE Design Automation Conference June 2002.
-
(2002)
Proceedings of the 39th ACM/IEEE Design Automation Conference
-
-
Cesario, W.1
Baghdadi, A.2
Gauthier, L.3
Lyonnard, D.4
Nicolescu, G.5
Paviot, Y.6
Yoo, S.7
Jerraya, A.A.8
Diaz-Nava, M.9
-
671
-
-
0344088129
-
Modeling and designing heterogenous systems
-
Springer, J. Cortadella, A. Yakovlev, G. Rozenberg (Eds.) Concurrency and Hardware Design
-
Balarin F., Lavagno L., Passerone C., Sangiovanni-Vincentelli A., Sgroi M., Watanabe Y. Modeling and designing heterogenous systems. LNCS2549
-
(2002)
LNCS2549
, pp. 228-273
-
-
Balarin, F.1
Lavagno, L.2
Passerone, C.3
Sangiovanni-Vincentelli, A.4
Sgroi, M.5
Watanabe, Y.6
-
673
-
-
35048840709
-
Constraints specification at higher levels of abstraction
-
Balarin F., Watanabe Y., Burch J., Lavagno L., Passerone R., Sangiovanni-Vincentelli A. Constraints specification at higher levels of abstraction. Proceeding of the 6th Annual IEEE International Workshop on High Level Design Validation and Test-HLDVT'01 November 2001.
-
(2001)
Proceeding of the 6th Annual IEEE International Workshop on High Level Design Validation and Test-HLDVT'01
-
-
Balarin, F.1
Watanabe, Y.2
Burch, J.3
Lavagno, L.4
Passerone, R.5
Sangiovanni-Vincentelli, A.6
-
675
-
-
0036049213
-
Concurrent execution semantics and sequential simulation algorithms for the metropolis metamodel
-
IEEE Comput. Soc. Press
-
Balarin F., Lavagno L., Passerone C., Sangiovanni-Vincentelli A., et al. Concurrent execution semantics and sequential simulation algorithms for the metropolis metamodel. Proceedings of the Tenth International Symposium on Hardware/Software Codesign 2002, 13-18. IEEE Comput. Soc. Press.
-
(2002)
Proceedings of the Tenth International Symposium on Hardware/Software Codesign
, pp. 13-18
-
-
Balarin, F.1
Lavagno, L.2
Passerone, C.3
Sangiovanni-Vincentelli, A.4
-
676
-
-
0003840975
-
-
Open SystemC Initiative
-
Open SystemC Initiative Functional Specification for SystemC 2.0 September 2001, avaliable at. http://www.systemc.org.
-
(2001)
Functional Specification for SystemC 2.0
-
-
-
678
-
-
84893733807
-
-
In Design Automation and Test in Europe, March 2003.
-
Chen, X., Hsieh, H., Balarin, F., and Watanabe, Y. Automatic generation of simulation monitors from quantitative constraint formula. In Design Automation and Test in Europe, March 2003.
-
Automatic generation of simulation monitors from quantitative constraint formula
-
-
Chen, X.1
Hsieh, H.2
Balarin, F.3
Watanabe, Y.4
-
680
-
-
0032680041
-
An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology
-
van der Wolf P., Lieverse P., Goel M., Hei D.L., Vissers K. An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology. Proceedings of the International Workshop on Hardware/Software Codesign May 1999, 33-37.
-
(1999)
Proceedings of the International Workshop on Hardware/Software Codesign
, pp. 33-37
-
-
van der Wolf, P.1
Lieverse, P.2
Goel, M.3
Hei, D.L.4
Vissers, K.5
-
681
-
-
0033682583
-
YAPI: Application Modeling for Signal Processing Systems
-
de Kock E.A., Essink G., Smits W.J.M., van der Wolf P., Brunel J.-Y., Kruijtzer W.M., Lieverse P., Vissers A.K. YAPI: Application Modeling for Signal Processing Systems. Proceedings of the Design Automation Conference June 2000.
-
(2000)
Proceedings of the Design Automation Conference
-
-
de Kock, E.A.1
Essink, G.2
Smits, W.J.M.3
van der Wolf, P.4
Brunel, J.-Y.5
Kruijtzer, W.M.6
Lieverse, P.7
Vissers, A.K.8
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