-
1
-
-
0028602659
-
Loop transformation methodology for fixed-rate video, image and telecom processing applications
-
San Francisco, CA, Aug.
-
F. Catthoor, W. Geurts, and H. De Man, "Loop transformation methodology for fixed-rate video, image and telecom processing applications," in Proc. Int. Conf. Applicat. Specific Array Processors, San Francisco, CA, Aug. 1994, pp. 427-438.
-
(1994)
Proc. Int. Conf. Applicat. Specific Array Processors
, pp. 427-438
-
-
Catthoor W Geurts, F.1
De Man, H.2
-
2
-
-
0029290289
-
Portable video-on-demand in wireless communication, special issue on Low power design
-
Apr.
-
T. Meng, B. Gordon, E. Tsern, and A. Hung, "Portable video-on-demand in wireless communication," special issue on "Low power design" Proc. IEEE, vol. 83, pp. 659-680, Apr. 1995.
-
(1995)
Proc. IEEE
, vol.83
, pp. 659-680
-
-
Meng, T.1
Gordon, B.2
Tsern, E.3
Hung, A.4
-
3
-
-
0012111580
-
Background memory management for the synthesis of algebraic algorithms on multi-processor DSP chips
-
Munich, Germany, Aug.
-
I. Verbauwhede, F. Catthoor, J. Vandewalle, and H. De Man, "Background memory management for the synthesis of algebraic algorithms on multi-processor DSP chips," in Proc. Int. Conf. VLSI, Munich, Germany, Aug. 1989, pp. 2098-2118.
-
(1989)
Proc. Int. Conf. VLSI
, pp. 2098-2118
-
-
Verbauwhede, I.1
Catthoor, F.2
Vandewalle, J.3
De Man, H.4
-
4
-
-
0003913538
-
-
Norwell, MA: Kluwer
-
F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle, Custom Memory Management Methodology - Exploration of Memory Organization for Embedded Multimedia System Design. Norwell, MA: Kluwer, 1998.
-
(1998)
Custom Memory Management Methodology - Exploration of Memory Organization for Embedded Multimedia System Design
-
-
Catthoor, F.1
Wuytack, S.2
De Greef, E.3
Balasa, F.4
Nachtergaele, L.5
Vandecappelle, A.6
-
5
-
-
0028727544
-
Dataflow-driven memory allocation for multi-dimensional processing systems
-
San Jose, CA, Nov.
-
F. Balasa, F. Catthoor, and H. De Man, "Dataflow-driven memory allocation for multi-dimensional processing systems," in Proc. IEEE Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 1994, pp. 31-34.
-
(1994)
Proc. IEEE Int. Conf. Computer-Aided Design
, pp. 31-34
-
-
Balasa, F.1
Catthoor, F.2
De Man, H.3
-
6
-
-
0027799223
-
Allocation of multiport memories for hierarchical data streams
-
Santa Clara, CA, Nov.
-
P. Lippens, J. Van Meerbergen, W. Verhaegh, and A. van der Werf, "Allocation of multiport memories for hierarchical data streams," in Proc. IEEE Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 1993, pp. 728-735.
-
(1993)
Proc. IEEE Int. Conf. Computer-Aided Design
, pp. 728-735
-
-
Lippens, P.1
Van Meerbergen, J.2
Verhaegh, W.3
Van Der Werf, A.4
-
7
-
-
0028076680
-
An algorithm for array variable clustering
-
Paris, France, Mar.
-
L. Ramachandran, D. Gajski, and V. Chaiyakul, "An algorithm for array variable clustering," in Proc. European Design Test Conf., Paris, France, Mar. 1994, pp. 262-266.
-
(1994)
Proc. European Design Test Conf.
, pp. 262-266
-
-
Ramachandran, L.1
Gajski, D.2
Chaiyakul, V.3
-
8
-
-
0028723004
-
Datapath synthesis
-
June
-
L. Stok, "Datapath synthesis," Integr. VLSI J., vol. 18, pp. 1-71, June 1994.
-
(1994)
Integr. VLSI J.
, vol.18
, pp. 1-71
-
-
Stok, L.1
-
9
-
-
0024682923
-
Force-directed scheduling for the behavioral synthesis of ASIC's
-
June
-
P. Paulin and J. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Trans. Computer-Aided Design, vol. 8, pp. 661-679, June 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.8
, pp. 661-679
-
-
Paulin, P.1
Knight, J.2
-
10
-
-
0029359416
-
Improved force-directed scheduling in high-throughput digital signal processing
-
Aug.
-
W. Verhaegh, P. Lippens, E. Aarts, J. Korst, J. van Meerbergen, and A. van der Werf, "Improved force-directed scheduling in high-throughput digital signal processing," IEEE Trans. Computer-Aided Design, vol. 14, pp. 945-960, Aug. 1995.
-
(1995)
IEEE Trans. Computer-Aided Design
, vol.14
, pp. 945-960
-
-
Verhaegh, W.1
Lippens, P.2
Aarts, E.3
Korst, J.4
Van Meerbergen, J.5
Van Der Werf, A.6
-
11
-
-
0002746388
-
-
Ph.D. dissertation, Dept. Elect. Eng., Eindhoven Univ. Technol., Eindhoven, The Netherlands, Oct.
-
W. Verhaegh, "Multidimensional periodic scheduling," Ph.D. dissertation, Dept. Elect. Eng., Eindhoven Univ. Technol., Eindhoven, The Netherlands, Oct. 1995.
-
(1995)
Multidimensional Periodic Scheduling
-
-
Verhaegh, W.1
-
12
-
-
0029518878
-
Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications
-
San Jose CA, Nov.
-
N. Passos and E. Sha, "Push-up scheduling: optimal polynomial-time resource constrained scheduling for multi-dimensional applications," in Proc. IEEE Int. Conf. Computer-Aided Design, San Jose CA, Nov. 1995, pp. 588-591.
-
(1995)
Proc. IEEE Int. Conf. Computer-Aided Design
, pp. 588-591
-
-
Passos, N.1
Sha, E.2
-
13
-
-
0027797653
-
Register allocation with instruction scheduling: A new approach
-
Jun.
-
S. Pinter, "Register allocation with instruction scheduling: A new approach," ACM SIGPLAN, vol. 28, pp. 248-257, Jun. 1993.
-
(1993)
ACM SIGPLAN
, vol.28
, pp. 248-257
-
-
Pinter, S.1
-
14
-
-
33747861129
-
Memory management for embedded network applications
-
to be published
-
S. Wuytack, J. da Silva, Jr., F. Catthoor, G. de Jong, and C. Ykman, "Memory management for embedded network applications," IEEE Trans. Computer-Aided Design, to be published.
-
IEEE Trans. Computer-Aided Design
-
-
Wuytack, S.1
Da Silva Jr., J.2
Catthoor, F.3
De Jong, G.4
Ykman, C.5
-
15
-
-
4243398061
-
-
Ph.D. dissertation, Dept. Elect. Eng., IMEC, Leuven, Belgium, Nov.
-
F. Balasa, "Background memory allocation for multi-dimensional signal processing," Ph.D. dissertation, Dept. Elect. Eng., IMEC, Leuven, Belgium, Nov. 1995.
-
(1995)
Background Memory Allocation for Multi-dimensional Signal Processing
-
-
Balasa, F.1
-
16
-
-
33747847831
-
A flexible 32 Kbit RAM generator for ASIC's based on process tolerant layout design
-
Grenoble, France, Dec.
-
G. Thierfelder et al., "A flexible 32 Kbit RAM generator for ASIC's based on process tolerant layout design," presented at the Int. Workshop Logic Architecture Synthesis, Grenoble, France, Dec. 1993.
-
(1993)
Int. Workshop Logic Architecture Synthesis
-
-
Thierfelder, G.1
-
17
-
-
0026103250
-
An area model for on-chip memories and its application
-
Feb.
-
J. M. Mulder, N. T. Quach, and M. J. Flynn, "An area model for on-chip memories and its application," IEEE J. Solid-State Circuits, vol. 26, pp. 98-105, Feb. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, pp. 98-105
-
-
Mulder, J.M.1
Quach, N.T.2
Flynn, M.J.3
-
18
-
-
0001868375
-
Global communication and memory optimizing transformations for low power systems
-
Napa, CA, Apr.
-
S. Wuytack, F. Catthoor, F. Franssen, L. Nachtergaele, and H. De Man, "Global communication and memory optimizing transformations for low power systems," in IEEE Int. Workshop Low Power Design, Napa, CA, Apr. 1994, pp. 203-208.
-
(1994)
IEEE Int. Workshop Low Power Design
, pp. 203-208
-
-
Wuytack, S.1
Catthoor, F.2
Franssen, F.3
Nachtergaele, L.4
De Man, H.5
-
19
-
-
0029530287
-
Background memory management for dynamic data structures intensive processing systems
-
San Jose, CA, Nov.
-
G. de Jong, B. Lin, C. Verdonck, S. Wuytack, and F. Catthoor, "Background memory management for dynamic data structures intensive processing systems," in Proc. Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 1995, pp. 515-520.
-
(1995)
Proc. Int. Conf. Computer-Aided Design
, pp. 515-520
-
-
De Jong, G.1
Lin, B.2
Verdonck, C.3
Wuytack, S.4
Catthoor, F.5
-
20
-
-
0031118953
-
Efficient general-purpose image compression with binary tree predictive coding
-
Apr.
-
J. Robinson, "Efficient general-purpose image compression with binary tree predictive coding," IEEE Trans. Image Processing, vol. 6, pp. 601-608, Apr. 1997.
-
(1997)
IEEE Trans. Image Processing
, vol.6
, pp. 601-608
-
-
Robinson, J.1
-
21
-
-
0030701111
-
Fast and extensive system-level memory exploration for ATM applications
-
Antwerp, Belgium, Sept.
-
P. Slock, S. Wuytack, F. Catthoor, and G. de Jong, "Fast and extensive system-level memory exploration for ATM applications," in Proc. 10th ACM/IEEE Int. Symp. System-Level Synthesis, Antwerp, Belgium, Sept. 1997, pp. 74-81.
-
(1997)
Proc. 10th ACM/IEEE Int. Symp. System-Level Synthesis
, pp. 74-81
-
-
Slock, P.1
Wuytack, S.2
Catthoor, F.3
De Jong, G.4
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