Optimization and control of VDD and VTH for low-power, high-speed CMOS design

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 28-34

  Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DELAY; POWER DISSIPATION; POWER REDUCTION; SUPPLY VOLTAGE;

ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS;

CMOS INTEGRATED CIRCUITS;

EID: 0036916198     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774577     Document Type: Conference Paper

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