System-level performance analysis for designing on-chip communication architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 6, 2001, Pages 768-783

  Lahiri, Kanishka ^a,b   Raghunathan, Anand ^a,c   Dey, Sujit ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c NEC LABORATORIES AMERICA   (United States)

Author keywords

Bus architectures; Communication architectures; On chip communication; Performance analysis; Simulation trace; System on chip

Indexed keywords

ON-CHIP COMMUNICATION ARCHITECTURE; SYSTEM-ON-CHIP; SYSTEM-ON-CHIP INTEGRATED CIRCUIT;

COMPUTATIONAL METHODS; COMPUTER SIMULATION; DATA TRANSFER; ELECTRIC NETWORK TOPOLOGY; ENERGY GAP; GRAPH THEORY; INTERCONNECTION NETWORKS; NETWORK PROTOCOLS; PERFORMANCE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035368837     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.924830     Document Type: Article

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