System-level power optimization: techniques and tools

ACM Transactions on Design Automation of Electronic Systems

Volumn 5, Issue 2, 2000, Pages 115-192

  Benini, Luca ^a,b   De Micheli, Giovanni ^a,b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33746995009     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/335043.335044     Document Type: Article

References (178)

1. ADVANCED MICRO DEVICES, 1998. AM29SLxxx low-voltage flash memories.
2. ADVANCED RISC MACHINES LTD., 1996. ARM software development toolkit version 2.11.
3. AGRAWAL, P. 1998. Energy conservation design techniques for mobile wireless VLSI systems. In Proceedings of the Computer Society Workshop on VLSI System-Level Design (Apr.), 34-39.
4. AHO, A., SETHI, R., AND ULLMAN, J. 1986. Compilers: Principles, Techniques, and Tools. Addison-Wesley, Reading, MA.
5. BAHAR, R. I., ALBERA, G., AND MANNE, S. 1998. Power and performance tradeoffs using various caching strategies. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED '98, Monterey, CA, Aug. 10-12), A. Chandrakasan and S. Kiaei, Eds. ACM Press, New York, NY, 64-69.
6. BAJWA, R. S., HIRAKI, M., KOJIMA, H., GORNY, D. J., NITTA, K, SHRIDHAR, A., SEKI, K., AND SASAKI, K. 1997. Instruction buffering to reduce power in processors for signal processing. IEEE Trans. Very Large Scale Integr. Syst. 5, 4, 417-424.
7. BAMBOS, N. 1998. Toward power-sensitive network architectures in wireless communications. IEEE Personal Commun. 5, 3 (June), 50-58.
8. BENINI, L. AND DE MICHELI, G. 1997. Dynamic Power Management: Design Techniques and CAD Tools. Kluwer Academic, Dordrecht, Netherlands.
9. BENINI, L., DE MICHELI, G., MACH, E., SCIUTO, D., AND SILVANO, C. 1997. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems. In Proceedings of the Great Lakes Symposium on VLSI (Mar.), 77-82.
10. BENINI, L., DE MICHELI, G., MACH, E., SCIUTO, D., AND SILVANO, C. 1998a. Address bus encoding techniques for system-level power optimization. In Proceedings of the Conference on Design, Automation and Test in Europe 98, 861-866.
11. BENINI, L., DE MICHELI, G., MACH, E., PONCINO, M., AND QUER, S. 1998b. Power optimization of core-based systems by address bus encoding. IEEE Trans. Very Large Scale Integr. Syst. 6, 4, 554-562.
12. BENINI, L., HODGSON, R., AND SIEGEL, P. 1998c. System-level power estimation and optimization. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED '98, Monterey, CA, Aug. 10-12), A. Chandrakasan and S. Kiaei, Eds. ACM Press, New York, NY, 173-178.
13. BENINI, L., MACH, A., MACH, E., PONCINO, M., AND SCARSI, R. 1999a. Synthesis of low-overhead interfaces for power-efficient communication over wide buses. In Proceedings of the Conference on Design Automation (June), 128-133.
14. BENINI, L., BOGLIOLO, A., PALEOLOGO, G., AND DE MICHELI, G. 1999b. Policy optimization for dynamic power management. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 18, 6 (June), 813-833.
15. BROWN, J. J., CHEN, D. Z., GREENWOOD, G. W., Hu, X., AND TAYLOR, R. W. 1997. Scheduling for power reduction in a real-time system. In Proceedings of the 1997 International Symposium on Low Power Electronics and Design (ISLPED '97, Monterey, CA, Aug. 18-20), B. Barton, M. Pedram, A. Chandrakasan, and S. Kiaei, Eds. ACM Press, New York, NY, 84-87.
16. BRUNVAND, E., NOWICK, S., AND YUN, K. 1999. Practical advances in asynchronous design and in asynchronous/synchronous interfaces. In Proceedings of the Conference on Design Automation (June), 104-109.
17. BURD, T. D. AND BRODERSEN, R. W. 1996. Processor design for portable systems. J. VLSI Signal Process. 13, 2/3, 203-221.
18. CATTHOOR, F., FRANSSEN, F., WUYTACK, S., NACHTERGAELE, L., AND DE MAN, H. 1994. Global communication and memory optimizing transformations for low power systems. In Proceed-ings of the International Workshop on Low Power Design, 203-208.
19. CATTHOOR, F., WUYTACK, S., DE GREEF, E., BALASA, F., NACHTERGAELE, L., AND VANDECAPPELLE, A. 1998a. Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design. Kluwer Academic, Dordrecht, Netherlands.
20. CATTHOOR, F., WUYTACK, S., DE GREEF, E., FRANSSEN, F., NACHTERGAELE, L., AND DE MAN, H. 1998b. System-level transformations for low-power data transfer and storage. In Low-Power CMOS Design, R. Chandrakasan and R. Brodersen, Eds. IEEE Press, Piscataway, NJ.
21. CHANDRAKASAN, A. P., POTKONJAK, M., MEHRA, R., RABAEY, J., AND BRODERSEN, R. 1995. Optimizing power using transformations. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 14, 1 (Jan.), 13-32.
22. CHANDRAKASAN, M. AND BRODERSEN, R. 1995. Low Power Digital CMOS Design. Kluwer Academic, Dordrecht, Netherlands.
23. CHANG, J.-M. AND PEDRAM, M. 1997. Energy minimization using multiple supply voltages. IEEE Trans. Very Large Scale Integr. Syst. 5, 4, 436-443.
24. CHAU, P. M. AND POWELL, S. R. 1992. Power dissipation of VLSI array processing systems. J. VLSI Signal Process. 4, 2/3 (May 1992), 199-212.
25. CHEN, J., JONE, W., WANG, J., Lu, H., AND CHEN, T. 1999. Segmented bus design for low-power systems. IEEE Trans. Very Large Scale Integr. Syst. 7, 1 (Mar.), 25-29.
26. CHUNG, E., BENINI, L., BOGLIOLO, A., AND DE MICHELI, G. 1999. Dynamic power management for non-stationary service requests. In Proceedings of the Conference on Design Automation and Test in Europe (Mar.), 77-81.
27. CHUNG, J. W., KAO, D.-Y., CHENG, C.-K, AND LIN, T.-T. 1995. Optimization of power dissipation and skew sensitivity in clock buffer synthesis. In Proceedings of the 1995 International Symposium on Low Power Design (ISLPD-95, Dana Point, CA, Apr. 23-26), M. Pedram, R. Brodersen, and K. Keutzer, Eds. ACM Press, New York, NY, 179-184.
28. CONTE, T., MENEZES, K., AND SATHAYE, S. 1995. Technique to determine power-efficient, high-performance superscalar processors. In Proceedings of the Hawaii International Conference on System Sciences (HICSS '95, Maui, Hawaii, Jan.), IEEE Computer Society Press, Los Alamitos, CA, 534-333.
29. COUMERI, S. L. AND THOMAS, D. E. 1998. Memory modeling for system synthesis. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED '98, Monterey, CA, Aug. 10-12), A. Chandrakasan and S. Kiaei, Eds. ACM Press, New York, NY, 179-184.
30. DALLY, W. J. AND POULTON, J. W. 1998. Digital Systems Engineering. Cambridge University Press, New York, NY.
31. DASGUPTA, A. AND KARRI, R. 1998. , High-reliability, low-energy microarchitecture synthesis. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 17, 12 (Dec.), 1273-1280.
32. DA SILVA, J. L., CATTHOOR, F., VERKEST, D., AND DE MAN, H. 1998. Power exploration for dynamic data types through virtual memory management refinement. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED '98, Monterey, CA, Aug. 10-12), A. Chandrakasan and S. Kiaei, Eds. ACM Press, New York, NY, 311-316.
33. DAVE, B., LAKSHMINARAYANA, G., AND JHA, N. 1999. COSYN: Hardware-software co-synthesis for heterogeneous distributed embedded systems. IEEE Trans. Very Large Scale Integr. Syst. 7, KMar.).
34. DEBNATH, G., DEBNATH, K., AND FERNANDO, R. 1995. The Pentium Processor-90/100, microarchitecture and low-power circuit design. In Proceedings of the IEEE International Conference on VLSI Design (Jan. 1995), IEEE Press, Piscataway, NJ, 185-190.
35. DE GREEF, E., CATTHOOR, F., AND DE MAN, H. 1998. Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems. IEEE Trans. Circuits Syst. Video Technol. 8, 6 (Oct.), 719-733.
36. DE MICHELI, G. AND GUPTA, R. 1997. Hardware/sofware co-design. Proc. IEEE 95, 3 (Mar.), 349-365.
37. DE MICHELI, G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc., New York, NY.
38. DOUGLIS, F., KRISHNAN, P., AND BERSHAD, B. 1995. Adaptive disk spin-down policies for mobile computers. In Proceedings of the 2nd USENIX Symposium on Mobile and LocationIndependent Computing, 121-137.
39. DOUGHERTY, W., PURSLEY, D., AND THOMAS, D. 1998. Instruction subsetting: Trading power for programmability. In Proceedings of the Computer Society Workshop on VLSI System-Level Design (Apr.), 42-47.
40. DUATO, J., YALAMANCHILI, S., AND Ni, L. 1997. Interconnection Networks. An Engineering Approach. IEEE Computer Society Press, Los Alamitos, CA.
41. ELLIS, C. 1999. The case for higher-level power management. In Proceedings of the IEEE Workshop on Hot Topics in Operating Systems (Mar.), IEEE Computer Society Press, Los Alamitos, CA, 162-167.
42. FARRAHI, A. H., TéLLEZ, G. E., AND SARRAFZADEH, M. 1995. Memory segmentation to exploit sleep mode operation. In Proceedings of the 32nd ACM/IEEE Conference on Design Automation (DAC '95, San Francisco, CA, June 12-16), B. T. Preas, Ed. ACM Press, New York, NY, 36-41. http:www.getridofme.com
43. FARRAHI, A. H. AND SARRAFZADEH, M. 1995. System'partitioning to maximize sleep time. In Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-95, San Jose, CA, Nov. 5-9), R. Rudell, Ed. IEEE Computer Society Press, Los Alamitos, CA, 452-455.
44. FLINN, J. AND SATYANARAYANAN, M. 1999. Energy-aware adaptation for mobile applications. In Proceedings of the ACM Symposium on Operating System Principles (Dec.), ACM Press, New York, NY, 48-63.
45. FURBER, S. 1997. ARM System Architecture. Addison-Wesley Publishing Co., Inc., Redwood City, CA.
46. GAJSKI, D. D., DUTT, N. D., Wu, A. C.-H., AND LIN, S. Y.-L. 1992. High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, Hingham, MA.
47. GAJSKI, D. D., VAHID, F., NARAYAN, S., AND GONG, J. 1994. Specification and Design of Embedded Systems. Prentice-Hall, Inc., Upper Saddle River, NJ.
48. GARY, S. AND IPPOLITO ET AL., P. 1994. PowerPC 603, a microprocessor for portable computers. IEEE Des. Test 11, 4 (Winter), 14-23.
49. GEBOTYS, C. 1997. Low energy memory and register allocation using network flow. In Proceedings of the 34th Conference on Design Automation ( DAC '97, Anaheim, CA, June), 435-440.
50. GlVARGIS, T. AND VAHID, F. 1998. Interface exploration for reduced power in core-based systems. In International Symposium on System-Level Synthesis (Dec.), 117-122.
51. GOLDING, R., BOSH, P., AND WlLKES, J. 1996. Idleness is not Sloth. Hewlett-Packard, Fort Collins, CO.
52. GONZALEZ, R. AND HOROWITZ, M. 1996. Energy dissipation in general purpose microprocessors. IEEE J. Solid-State Circuits 31, 9 (Sept.), 1277-1284.
53. GOOSSENS, G., PAULIN, P., VAN PRAET, J., LANNEER, D., GUERTS, W., KIFLI, A., AND LIEM, C. 1997. Embedded software in real-time signal processing systems: Design technologies. Proc. IEEE 85, 3 (Mar.), 436-454.
54. GOVIL, K, CHAN, E., AND WASSERMAN, H. 1995. Comparing algorithm for dynamic speedsetting of a low-power CPU. In Proceedings of the First Annual International Conference on Mobile Computing and Networking (MOBICOM '95, Berkeley, CA, Nov. 13-15), B. Awerbuch and D. Duchamp, Eds. ACM Press, New York, NY, 13-25.
55. GOWAN, M. K., BIRO, L. L., AND JACKSON, D. B. 1998. Power considerations in the design of the Alpha 21264 microprocessor. In Proceedings of the 35th Annual Conference on Design Automation (DAC '98, San Francisco, CA, June 15-19), B. R. Chawla, R. E. Bryant, and J. M. Rabaey, Eds, ACM Press, New York, NY, 726-731.
56. GUERRA, L., POTKONJAK, M., AND RABAEY, J. 1998. A methodology for guided behavioral-level optimization. In Proceedings of the 35th Annual Conference on Design Automation (DAC '98, San Francisco, CA, June 15-19), B. R. Chawla, R. E. Bryant, and J. M. Rabaey, Eds, ACM Press, New York, NY, 309-314.
57. GUTNIK, V. AND CHANDRAKASAN, A. P. 1997. Embedded power supply for low-power DSP. IEEE Trans. Very Large Scale Integr. Syst. 5, 4, 425-435.
58. HAJJ, N. B. I., STAXIOULIS, G., BELLAS, N., AND POLYCHRONOPOULOS, C. 1998. Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED '98, Monterey, CA, Aug. 10-12), A. Chandrakasan and S. Kiaei, Eds. ACM Press, New York, NY, 70-75.
59. HARRIS ET AL., E. 1995. Technology directions for portable computers. Proc. IEEE 83, 4 (Apr.), 636-657.
60. HASEGAWA, A., KAWASAKI, I., YAMADA, K., YOSHIOKA, S., YOSHIOKA, S., KAWASAKI, S., AND BlSWAS, P. 1995. SH3: High code density, low power. IEEE Micro 15, 5 (Dec.).
61. HEGDE, R. AND SHANBHAG, N. R. 1998. Energy-efficiency in presence of deep submicron noise. In Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '98, San Jose, CA, Nov. 8-12), H. Yasuura, Ed. ACM Press, New York, NY, 228-234.
62. HELMBOLD, D. P., LONG, D. D. E., AND SHERROD, B. 1996. A dynamic disk spin-down technique for mobile computing. In Proceedings of the 2nd Annual International Conference on Mobile Computing and Networking (MOBICÖM '96, Rye, NY, Nov. 10-12), H. Ahmadi, R. H. Katz, I. F. Akyildz, and Z. J. Haas, Eds. ACM Press, New York, NY, 130-142.
63. HEMANI, A., MEINCKE, T., KUMAR, T., OLSSON, T., NILSSON, P., OBERG, J., ELLERVEE, P., AND LUNDQVIST, D. 1999. Lowering power consumption in clock by using globally asynchronous locally synchronous design style. In Proceedings of the Conference on Design Automation (June), 873-878.
64. HENKEL, J. 1999. A low-power hardware/software partitioning approach for core-based embedded systems. In Proceedings of the Conference on Design Automation (June), 122-127.
65. HENNESSY, J. L. AND PATTERSON, D. A. 1996. Computer Architecture: A Quantitative Approach. 2nd ed. Morgan Kaufmann Publishers Inc., San Francisco, CA. ,
66. HONG, L, POTKONJAK, M., AND KARRI, R. 1997. Power optimization using divide-and-conquer techniques for minimization of the number of operations. In Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '97, San Jose, CA, Nov. 9-13), R. H. J. M. Otten and H. Yasuura, Eds. IEEE Computer Society, Washington, DC, 108-111.
67. HONG, I., KIROVSKI, D., Qu, G., POTKONJAK, M., AND SRIVASTAVA, M. B. 1998. Power optimization of variable voltage core-based. systems. In Proceedings of the 35th Annual Conference on Design Automation (DAC '98, San Francisco, CA, June 15-19), B. R. Chawla, R. E. Bryant, and J. M. Rabaey, Eds, ACM Press, New York, NY, 176-181.
68. HONG, I., POTKONJAK, M., AND SRIVASTAVA, M. B. 1998. On-line scheduling of hard real-time tasks on variable voltage processor. In Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '98, San Jose, CA, Nov. 8-12), H. Yasuura, Ed. ACM Press, New York, NY, 653-656.
69. HONG, L, Qu, G., AND POTKONJAK, M. 1998. Synthesis techniques for low-power hard real-time systems on variable voltage processors. In Proceedings of the 19th IEEE Symposium on Real-Time Systems (Madrid, Spain, Dec.), IEEE Computer Society Press, Los Alamitos, CA, 178-187.
70. HWANG, C.-H. AND Wu, A. C.-H. 1997. A predictive system shutdown method for energy saving of event-driven computation. In Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '97, San Jose, CA, Nov. 9-13), R. H. J. M. Otten and H. Yasuura, Eds. IEEE Computer Society, Washington, DC, 28-32.
71. INTEL. 1998. SA-1100 Microprocessor Technical Reference Manual. Intel Corp., Santa Clara, CA.
72. ISHIHARA, T. AND YASUURA, H. 1998. Voltage scheduling problem for dynamically variable voltage processors. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED '98, Monterey, CA, Aug. 10-12), A. Chandrakasan and S. Kiaei, Eds. ACM Press, New York, NY, 197-202.
73. ISHIHARA, T. AND YASUURA, M. 1998. Power-Pro: Programmable power management architecture. In Proceedings of the on Asia and South Pacific Design Automation (Feb.), 321-322.
74. ITOH, K., SASAKI, K., AND NAKAGOME, Y. 1995. Trends in low-power RAM circuit technologies. Proc. IEEE 83, 4 (Apr.), 524-543.
75. JOHNSON, M. AND ROY, K. 1996. Optimal selection of supply voltages and level-conversion during data-path scheduling under resource constraints [AUTHOR: This citation does NOT appearin this Proceedings. We need CORRECT info.]. In Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '96, San Jose, CA, Nov. 10-14), R. A. Rutenbar and R. H. J. M. Otten, Eds. IEEE Computer Society Press, Los Alamitos, CA.
76. JOUPPI, N. AND WILTON, N. 1996. CACTI: An enhanced cache access and cycle time model. IEEE J. Solid-State Circuits 31, 5 (May), 677-688.
77. JUAN, T., LANG, T., AND NAVABRO, J. J. 1997. Reducing TLB power requirements. In Proceedings of the 1997 International Symposium on Low Power Electronics and Design (ISLPED '97, Monterey, CA, Aug. 18-20), B. Barton, M. Pedram, A. Chandrakasan, and S. Kiaei, Eds. ACM Press, New York, NY, 196-201.
78. KALAMBUR, A. AND IRWIN, M. J. 1997. An extended addressing mode for low power. In Proceedings of the 1997 International Symposium on Low Power Electronics and Design (ISLPED '97, Monterey, CA, Aug. 18-20), B. Barton, M. Pedram, A. Chandrakasan, and S. Kiaei, Eds. ACM Press, New York, NY, 208-213.
79. KAMELE, M. B. AND CHOSE, K. 1997. Analytical energy dissipation models for low-power caches. In Proceedings of the 1997 International Symposium on Low Power Electronics and Design (ISLPED '97, Monterey, CA, Aug. 18-20), B. Barton, M. Pedram, A. Chandrakasan, and S. Kiaei, Eds. ACM Press, New York; NY, 143-148.
80. KAPOOR, B. 1998. Low power memory architectures for video applications. In Proceedings of the Great Lakes Symposium on VLSI (Feb.), 2-7.
81. KARLIN, A., MANASSE, M., McGEOCH, L., AND OWICKI, S. 1994. Competitive randomized ' algorithms for nonuniform problems. Algorithmica 11, 6 (June), 542-571.
82. KlM, D. AND CHOI, K. 1997. Power-conscious high level synthesis using loop folding. In Proceedings of the 34th Annual Conference on Design Automation (DAG '97, Anaheim, CA, June 9-13), E. J. Yoffa, G. De Micheli, and J. M. Rabaey, Eds. ACM Press, New York, NY, 441-445.
83. KIN, J., GUPTA, M., AND MANGIONE-SMITH, W. H. 1997. The filter cache: an energy efficient memory structure. In Proceedings of the 30th Annual IEEE I ACM International Symposium on Microarchitecture (MICRO 30, Research Triangle Park, NC, Dec. 1-3), M. Smotherman and T. Conte, Eds. IEEE Computer Society Press, Los Alamitos, CA, 184-193.
84. KIN, J., LEE, C., MANGIONE-SMITH, W., AND POTKONJAK, M. 1999. Power efficient mediaprocessors: Design space exploration. In Proceedings of the Conference on Design Automation (June), 321-326.
85. KIROVSKI, D., LEE, C., POTKONJAK, M., AND MANGIONE-SMITH, W. 1998. Synthesis of power efficient systems-on-silicon. In Proceedings of the Conference on Asian and South Pacific Design Automation (Feb.), 557-562.
86. KIROVSKI, D. AND POTKONJAK, M. 1997. System-level synthesis of low-power hard real-time systems. In Proceedings of the 34th Annual Conference on Design Automation (DAG '97, Anaheim, CA, June 9-13), E. J. Yoffa, G. De Micheli, and J. M. Rabaey, Eds. ACM Press, New York, NY, 697-702.
87. Ko, U., BALSARA, P. T., AND NANDA, A. K. 1998. Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. Very Large Scale Integr. Syst. 6, 2, 299-308.
88. KOMATSH, S., IKEDA, M., AND ASADA, K. 1999. Low power chip interface based on bus data encoding with adaptive code-book method. In Proceedings of the Great Lakes Symposium on VLSI, 368-371.
89. KRISHNAN, P., LONG, P., AND VOTER, J. 1995. Adaptive disk spindown via optimal rent-to-buy in probabilistic environments. In Proceedings of the 12th International Conference on Machine Learning (Lake Tahoe, CA), 322-330.
90. KULKARNI, C., CATTHOOR, F., AND DE MAN, H. 1998. Code transformations for low power caching in embedded multimedia processors. In Proceedings of the First Merged IPPSI SPDP Symposium on Parallel and Distributed Processing (IPPS/SPDP '98, Mar.), 23-26.
91. KUMAR, N.( KATKOORI, S., RADER, L., AND VEMURI, R. 1995. Profile-driven behavioral synthesis for low-power VLSI systems. IEEE Des. Test 12, 3 (Fall 1995), 70-84.
92. LAKSHMINARAYANA, G., RAGHUNATHAN, A., KHOURI, K., JHA, N., AND DEY, S. 1999. Common-case computation: A high-level technique for power and performance optimization. In Proceedings of the Conference on Design Automation (June), 56-61.
93. LEE, M. T.-C., FUJITA, M.f TIWARI, V., AND MALIK, S. 1997. Power analysis and minimization techniques for embedded DSP software. IEEE Trans. Very Large Scale Integr. Syst. 5, 1, 123-135.
94. LEE ET AL., W. 1997. A 1-V programmable DSP for wireless communications. IEEE J. Solid-State Circuits 32, 11 (Nov.), 1766-1776.
95. LEE, E. AND SANGIOVANNI-VINCENTELLI, A. 1998. A framework for comparing models of computation. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 17, 12 (Dec.), 1217-1229.
96. LEKATSAS, H. AND WOLF, W. 1998. Code compression for embedded systems. In Proceedings of the 35th Annual Conference on Design Automation (DAG '98, San Francisco, CA, June 15-19), B. R. Chawla, R. E. Bryant, and J. M. Rabaey, Eds, ACM Press, New York, NY, 516-521.
97. Li, Y. AND HENKEL, J.-R. 1998. A framework for estimation and minimizing energy dissipation of embedded HW/SW systems. In Proceedings of the 35th Annual Conference on Design Automation (DAG '98, San Francisco, CA, June 15-19), B. R. Chawla, R. E. Bryant, and J. M. Rabaey, Eds, ACM Press, New York, NY, 188-193.
98. LIAO, S., DEVADAS, S., AND KEUTZER, K. 1998. Code density optimization for embedded DSP processors using data compression techniques. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 17,1 (July), 601-608.
99. LIDSKY, D. AND RABAEY, J. M. 1996. Early power exploration-a World Wide Web application. In Proceedings of the 33rd Annual Conference on Design Automation (DAG '96, Las Vegas, NV, June 3-7), T. P. Pennino and E. J. Yoffa, Eds. ACM Press, New York, NY, 27-32.
100. LIDSKY, D. AND RABAEY, J. 1994. Low-power design of memory intensive functions. In Proceedings of the IEEE Symposium on Low Power Electronics (Sept.), IEEE Computer Society Press, Los Alamitos, CA, 16-17.
101. LITCH, T. AND SLATON, J. 1998. Portable communications. IEEE Micro 18, 2 (Apr.), 48-55.
102. LORCH, J. AND SMITH, A. 1998. Software strategies for portable computer energy management. IEEE Personal Commun. 5, 3 (June).
103. LORCH, J. R. AND SMITH, A. J. 1997. Scheduling techniques for reducing processor energy use in MacOS. Wireless Networks 3, 5, 311-324.
104. Lu, Y., CHUNG, E. Y., IMUNI, T., BENINI, L., AND DE MICHELI, G. 2000. Quantitative comparison of power management algorithms, DATE. In Proceedings of the Conference on Design Automation and Test in Europe (Mar.),
105. LUDWIG, J., NAWAB, H., AND CHANDRAKASAN, A. 1996. Low-power digital filtering using approximate processing. IEEE J. Solid-State Circuits 31, 3 (Mar.), 395-399.
106. MACH, E., PEDRAM, M., AND SOMENZI, F. 1998. High-level power modeling, estimation and optimization. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 17, 11 (Nov.), 1061-1079.
107. MARTIN, T. AND SEWIOREK, D. 1999. The impact of battery capacity and memory bandwith on CPU speed-setting: A case study. In Proceedings of the International Symposium on Low Power Electronics and Design (June), 200-205.
108. MARTIN, T. AND SIEWIOREK, D. 1996. A power metric for mobile systems. In Proceedings of the 1996 International Symposium on Low Power Electronics and Design (ISLPED '96, Monterey, CA, Aug 12-14), M. Horowitz, J. Rabaey, B. Barton, and M. Pedram, Eds. IEEE Press, Piscataway, NJ, 37-42.
109. MEHRA, R., GUERRA, L. M., AND RABAEY, J. M. 1996. Low-power architectural synthesis and the impact of exploiting locality. J. VLSI Signal Process. 13, 2/3, 239-258.
110. MEHRA, R., GUERRA, L., AND RABAEY, J. 1997. A partitioning scheme for optimizing interconnect power. IEEE J. Solid-State Circuits 32, 3 (Mar.), 433-443.
111. MEHTA, H., OWENS, R. M., AND IRWIN, M. J. 1996. Some issues in Gray code addressing. In Proceedings of the Great Lakes Symposium on VLSI (Ames, IA), IEEE Computer Society Press, Los Alamitos, CA, 178-180.
112. MEHTA, H., OWENS, R. M., IRWIN, M. J., CHEN, R., AND GHOSH, D. 1997. Techniques for low energy software. In Proceedings of the 1997 International Symposium on Low Power Electronics and Design (ISLPED '97, Monterey, CA, Aug. 18-20), B. Barton, M. Pedram, A. Chandrakasan, and S. Kiaei, Eds. ACM Press, New York, NY, 72-75.
113. MENDL, J. 1995. Low power microelectronics: Retrospect and prospect. Proc. IEEE 83, 4 (Apr.), 619-635.
114. MENG, T., GORDON, B., TSENG, E., AND HUNG, A. 1995. Portable video-on-demand in wireless communication. Proc. IEEE 83, 4 (Apr.), 659-690.
115. MICROSOFT AND TOSHIBA. 1996. Advanced configuration and power interface specification. Tech. Rep.
116. MICROSOFT. 1997. OnNow: the evolution of the PC platform. Microsoft Press, Redmond, WA.
117. MONTEIRO, J., DEVADAS, S., ASHAR, P., AND MAUSKAR, A. 1996. Scheduling techniques to enable power management. In Proceedings of the 33rd Annual Conference on Design Automation (DAC '96, Las Vegas, NV, June 3-7), T. P. Pennino and E. J. Yoffa, Eds. ACM Press, New York, NY, 349-352.
118. MUCHNICK, S. S. 1997. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers Inc., San Francisco, CA.
119. MUSOLL, E., LANG, T., AND CORTADELLA, J. 1998. Working-zone encoding for reducing the energy in microprocessor address buses. IEEE Trans. Very Large Scale Integr. Syst. 6, 4, 568-572.
120. MUTOH, S., SHIGEMATSU, S., MATSUYA, Y., FUKUDA, H., KANEKO, T., AND YMIADA, J. 1996. A1-V multithreshold-voltage CMOS digital signal processor for mobile phone applications. IEEE J. Solid-State Circuits 31, 11 (Nov.), 1795-1802.
121. NACHTERGAELE, L., MOOLENAAR, D., VANHOOF, B., CATTHOOR, F., AND DE MAN, H. 1998. System-level power optimization of video codecs on embedded cores: a systematic approach. J. VLSI Signal Process. 18, 2, 89-109.
122. NAMGOONG, W., Yu, M., AND MENG, T. 1997. A high-efficiency variable-voltage CMOS dynamic DC-DC switching regulator. In Proceedings of the IEEE 'International Conference on Solid-State Circuits, IEEE Computer Society Press, Los Alamitos, CA, 380-381.
123. NAWAB, S. H., OPPENHEIM, A. V., CHANDRAKASAN, A. P., WINOGRAD, J. M., AND LUDWIG, J. T. 1997. Approximate signal processing. J. VLSI Signal Process. 15, 1-2, 177-200.
124. NIELSEN, L. S. AND NiESSEN, C. 1994. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Trans. Very Large Scale Integr. Syst. 2, 4 (Dec. 1994), 391-397.
125. NlSHITANI, T. 1999. Low-power architectures for programmable multimedia processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E82-A, 2 (Feb.), 184-196.
126. PANDA, P. AND DUTT, N. 1999. Low-power memory mapping through reducing address bus activity. IEEE Trans. Very Large Scale Integr. Syst. 7, 3 (Sept.), 309-320.
127. PANWAR, R. AND RENNELS, D. 1995. Reducing the frequency of tag compares for low power I-cache design. In Proceedings of the 1995 International Symposium on Low Power Design (ISLPD-95, Dana Point, CA, Apr. 23-26), M. Pedram, R. Brodersen, and K. Keutzer, Eds. ACM Press, New York, NY, 57-62.
128. PEDRAM, M. 1996. Power minimization in 1C design: Principles and applications. ACM Trans. Des. Autom. Electron. Syst. l, l, 3-56.
129. PEDRAM, M. AND VAISHNAV, H. 1997. Power optimization in VLSI layout: A survey. J. VLSI Signal Process. 15, 3, 221-232.
130. PEDRAM, M. AND Wu, Q. 1999. Design considerations for battery-powered electronics. In Proceedings of the Conference on Design Automation (June), 861-866.
131. PERING, T., BURD, T., AND BRODERSEN, R. 1998. The simulation and evaluation of dynamic voltage scaling algorithms. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED '98, Monterey, CA, Aug. 10-12), A. Chandrakasan and S. Kiaei, Eds. ACM Press, New York, NY, 76-81.
132. OTKONJAK, M. AND RABAEY, M. 1999. Algorithm selection: A quantitative optimization-intensive approach. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 18, 5 (May), 524-532.
133. PUTERMAN, M. 1994. Finite Markov Decision Processes. John Wiley and Sons, Inc., New York, NY.
134. Qu, G. AND POTKONJAK, M. 1998. Techniques for energy minimization of communication pipelines. In Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '98, San Jose, CA, Nov. 8-12), H. Yasuura, Ed. ACM Press, New York, NY, 597-600.
135. RABAEY, J. AND PEDRAM, M. 1996. Low Power Design Methodologies. Kluwer Academic, Dordrecht, Netherlands.
136. RAGHUNATHAN, A. AND JHA, N. 1997. SCALP: An iterative improvement-based low-power datapath synthesis algorithm. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 14,11 (Nov.), 1260-1277.
137. RAGHUNATHAN, A., JHA, N., AND DEY, S. 1998. High-Level Power Analysis and Optimization. Kluwer Academic, Dordrecht, Netherlands.
138. RAGHUNATHAN, A., DEY, S., AND JHA, N. 1999. Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. Comput.-Aided Des. 18, 8 (Aug.), 1114-1131.
139. RAJE, S. AND SARRAFZADEH, M. 1995. Variable voltage scheduling. In Proceedings of the 1995 International Symposium on Low Power Design (ISLPD-95, Dana Point, CA, Apr. 23-26), M. Pedram, R. Brodersen, and K. Keutzer, Eds.. ACM Press, New York, NY, 9-14.
140. RAMPRASAD, S., SHANBHAG, N., AND HAJJ, I. 1998. Signal coding for low power: Fundamental limits and practical realizations. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Computer Society Press, Los Alamitos, CA.
141. Ross, S. 1997. Introduction to Probability Models. Academic Press, Inc., New York, NY.
142. SACHA, J. AND IRWIN, M. 1998. Number representation for reducing switching capacitance in subband coding. In Proceedings of the International Conference on Acoustics, Speech and Signal Processing (May), 12-15.
143. SAIED, R. AND CHAKRABARTI, C. 1996. Scheduling for minimizing the number of memory accesses in low power applications. In VLSI Signal Processing 169-178.
144. SAN MARTIN, R. AND KNIGHT, J. 1996. Optimizing power in ASIC behavioral synthesis. IEEE Des. Test 13, 2, 58-70.
145. SEGARS, S., CLARKE, K, AND GOUDGE, L. 1995. Embedded control problems, thumb and the ARM7TDMI. IEEE Micro 15, 5 (Dec.), 22-30.
146. SHIN, Y. AND CHOI, K. 1999. Power conscious fixed priority scheduling for hard real-time systems. In Proceedings of the Conference on Design Automation (June), 134-139.
147. SHIUE, W. AND CHAKRABARTI, C. 1999. Memory exploration for low power, embedded systems. In Proceedings of the Conference on Design Automation (June), 140-145.
148. SIMUNIC, T., BENINI, L., AND DE MICHELI, G. 1999. Cycle-accurate simulation of energy consumption in embedded systems. In Proceedings of the Conference on Design Automation (June), 867-872.
149. SIMUNIC, T., BENINI, L., AND DE MICHELI, G. 1999. Energy-efficient design of battery-powered embedded systems. In Proceedings of the International Symposium on Low Power Electornics and Design (June), 212-217.
150. SRATAKOS, A., SANDERS, S., AND BRODERSEN, R. 1994. A low-voltage CMOS DC-DC converter for a portable battery-operated system. In Proceedings of the IEEE Conference on Power Electronics Specialists, IEEE Computer Society Press, Los Alamitos, CA, 619-626.
151. SRIVASTAVA, M. B., CHANDRAKASAN, A. P., AND BRODERSEN, R. W. 1996. Predictive system shutdown and other architectural techniques for energy efficient programmable computation. IEEE Trans. Very Large Scale Integr. Syst. 4, 1, 42-55.
152. SRIVASTAVA, M. B. AND POTKONJAK, M. 1996. Power optimization in programmable processors and ASIC implementations of linear systems: Transformation-based approach. In Proceed-ings of the 33rd Annual Conference on Design Automation (DAC '96, Las Vegas, NV, June 3-7), T. P. Pennine and E. J. Yoffa, Eds. ACM Press, New York, NY, 343-348.
153. STAN, M. R. AND BURLESON, W. P. 1995. Bus-invert coding for low-power I/O. IEEE Trans. Very Large Scale Integr. Syst. 3, 1 (Mar. 1995), 49-58.
154. STAN, M. R. AND BURLESON, W. P. 1997. Low-power encodings for global communication in CMOS VLSI. IEEE Trans. Very Large Scale Integr. Syst. 5, 4, 444-455.
155. STEMM, M. AND KATZ, R. 1997. Measuring and reducing energy consumption of network interfaces in hand-held devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E80-B, 8 (Aug.), 1125-1131.
156. Su, C. L., Tsui, C. Y., AND DESPAIN, A. M. 1994. Saving power in the control path of embedded processors. IEEE Des. Test 11, 4 (Winter), 24-30.
157. Su, C.-L. AND DESPAIN, A. M. 1995. Cache'design trade-offs for power and performance optimization: a case study. In Proceedings of the 1995 International Symposium on Low Power Design (ISLPD-95, Dana Point, CA, Apr. 23-26), M. Pedram, R. Brodersen, and K. Keutzer, Eds. ACM Press, New York, NY, 63-68.
158. SUZUKI ET AL., K. 1997. A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS. In Proceedings of the Conference on Custom Integrated Circuits (May), 112-118.
159. TIWARI, V., MALIK, S., AND WOLFE, A. 1994. Power analysis of embedded software: a first step towards software power minimization. IEEE Trans. Very Large Scale Integr. Syst. 2, 4 (Dec. 1994), 437-445.
160. TIWARI, V., MALIK, S., WOLFE, A., AND LEE, M. T.-C. 1996. Instruction level power analysis and optimization of software. J. VLSI Signal Process. 13, 2/3, 223-238.
161. TIWARI, V., SINGH, D., RAJGOPAL, S., MEHTA, G., PATEL, R., AND BAEZ, F. 1998. Reducing power in high-performance microprocessors. In Proceedings of the 35th Annual Conference on Design Automation (DAC '98, San Francisco, CA, June 15-19), B. R. Chawla, R. E. Bryant, and J. M. Rabaey, Eds, ACM Press, New York, NY, 732-737.
162. TOMIYAMA, H., ISHIHARA, T., INDUE, A., AND YASUURA, H. 1998. Instruction
163. USAMI, K. AND IGARASHI ET AL., M. 1998. Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE J. Solid-State Circuits 33, 3 (Mar.), 463-472.
164. USAMI, K., IGARASHI, M., ISHIKAWA, T., KANAZAWA, M., TAKAHASHI, M., HAMADA, M., ARAKIDA, H., TERAZAWA, T., AND KURODA, T. 1998. Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques. In Proceedings of the 35th Annual Conference on Design Automation (DAC '98, San Francisco, CA, June 15-19), B. R. Chawla, R. E. Bryant, and J. M. Rabaey, Eds, ACM Press, New York, NY, 483-488.
165. VERBAUWHEDE, I. AND TOURIGUIAN, M. 1998. A low power DSP engine for wireless communications. J. VLSI Signal Process. 18, 2, 177-186.
166. VITTOZ, E. 1994. Low power microelectronics: Ways to approach the limits. In Proceedings of the International Conference on Solid-State Circuits (Jan.), 14-18.
167. WAN, M., ICHIKAWA, Y., LIDSKY, D., AND RABAEY, J. 1998. An energy conscious methodology for aarly design exploration of heterogeneous DSPs. In Proceedings of the Conference on Custom Integrated Circuits (May), 111-117.
168. WEI, G. AND HOROWITZ, M. 1996. A low power switching power supply for self-clocked systems. In Proceedings of the 1996 International Symposium on Low Power Electronics and Design (ISLPED '96, Monterey, CA, Aug 12-14), M. Horowitz, J. Rabaey, B. Barton, and M. Pedram, Eds. IEEE Press, Piscataway, NJ, 313-317.
169. WEISER, M., WELCH, B., DEMERS, A., AND SHENKER, S. 1994. Scheduling for reduced CPU energy. In Proceedings of the First USENIX Symposium on Operating Systems Design and Implementation (Monterey, CA, May), USENIX Assoc., Berkeley, CA, 13-23.
170. WINZKER, M. 1998. Low-power arithmetic for the processing of video signals. IEEE Trans. Very Large Scale Integr. Syst. 6, 3 (Sept.).
171. WOLF, W. 1994. Hardware-software co-design of embedded systems. Proc. IEEE 82, 7 (July 1994), 967-989.
172. WOLFE, A. 1996. Issues for low-power CAD tools: A system-level design study. J. Des. Autom. Embedded Syst. l, 4, 315-332.
173. WUYTACK, S., CATTHOOR, F., AND DE MAN, H. 1997. Transforming set data types to power optimal data structures. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 15, 6 (June), 619-629.
174. WUYTACK, S., DJGUET, J.-P., CATTHOOR, F. V. M., AND DE MAN, H. J. 1998. Formalized methodology for data reuse exploration for low-power hierarchical memory mappings. IEEE Trans. Very Large Scale Integr. Syst. 6, 4, 529-537.
175. YOSHIDA, Y., SONG, B.-Y., OKUHATA, H., ONOYE, T., AND SHIRAKAWA, I. 1997. An object code compression approach to embedded processors. In Proceedings of the 1997. International Symposium on Low Power Electronics and Design (ISLPED '97, Monterey,' CA, Aug. 18-20), B. Barton, M. Pedram, A. Chandrakasan, and S. Kiaei, Eds. ACM Press, New York, NY, 265-268.
176. ZHANG, H. AND RABAEY, J. 1998. Low-swing interconnect interface circuits. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED '98, Monterey, CA, Aug. 10-12), A. Chandrakasan and S. Kiaei, Eds. ACM Press, New York, NY, 161-166.
177. ZHANG, Y., Hu, X., AND CHEN, D. 1999. Low energy register allocation beyond basic blocks. In Proceedings of the International Symposium on Circuits and Systems (June), 290-293.
178. ZYUBAN, V. AND KOGGE, P. 1998. The energy complexity of register files. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED '98, Monterey, CA, Aug. 10-12), A. Chandrakasan and S. Kiaei, Eds. ACM Press, New York, NY, 305-310.