Power optimization of variable voltage core-based systems

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 176-181

  Hong, Inki ^a   Kirovski, Darko ^a   Qu, Gang ^a   Potkonjak, Miodrag ^a   Srivastava, Mani B ^a  

^a Los Angeles   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERACTIVE COMPUTER SYSTEMS; OPTIMIZATION; PERSONAL COMPUTING; REAL TIME SYSTEMS; SCHEDULING; SYSTEM-ON-CHIP; BUFFER STORAGE; COMPUTER HARDWARE; ENERGY UTILIZATION; HEURISTIC METHODS; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS;

COMMUNICATION APPLICATION; COMMUNICATION DEVICE; INDUSTRIAL STRENGTH; LOWER-POWER CONSUMPTION; POWER OPTIMIZATION; SCHEDULING TECHNIQUES; SYNTHESIS TECHNIQUES; TARGET APPLICATION;

INTEGRATED CIRCUIT DESIGN; COMPUTER SYSTEMS PROGRAMMING;

VARIABLE VOLTAGE CORE-BASED SYSTEMS;

EID: 0031624030     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277088     Document Type: Conference Paper

References (19)

1. A. Chandrakasan, V. Gutnik, and T. Xanthopoulos. Data driven signal processing: An approach for energy efficient computing. In International Symposium on Law Power Electronics and Design, pages 344-352, 1996.
2. A. P. Chandrakasan, S. Sheng, and R.W. Broderson. Low- power CMOS digital design. IEEE Journal of Solid-State Circuits, 27(4):473-484, 1992.
3. J.-M. Chang and M. Pedram. Energy minimization using multiple supply voltages. In International Symposium on Low Power Electronics and Design, pages 157-162, 1996.
4. http://infopad.eecs.berkeley.edu/CIC/.
5. M.R. Garey and D.S. Johnson. Computer and Intractability: A Guide to the theory of NP-Completeness. W. H. Freeman & Co., New York, NY, 1979.
6. R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31(9): 1277-1284, 1996.
7. K. Govil, E. Chan, and H. Wasserman. Comparing algorithms for dynamic speed-setting of a low-power CPU. In ACM International Conference on Mobile Computing and Networking, pages 13-25, 1995.
8. C. Hwang and A.C.-H. Wu. A predictive system shutdown method for energy saving of event-driven computation. In IEEE/ACM International Conference on Computer-Aided Design, pages 28-32, 1997.
9. M. C. Johnson and K. Roy. Datapath scheduling with multiple supply voltages and level converters. ACM Transactions on Design Automation of Electronic Systems, 2(3), 1997.
10. D. Kirovski, C. Lee, W. Mangione-Smith, and M. Potkonjak. Application-driven synthesis of core-based systems. In IEEE/ACM International Conference on Computer-Aided Design, pages 104-107, 1997.
11. D. Kirovski, C. Lee, W. Mangione-Smith, and M. Potkonjak. Synthesis of power efficient systems-on-silicon. In Asia and South Pacific Design Automation Conference, 1998.
12. Y.-R. Lin, C.-T. Hwang, and A.C.-H Wu. Scheduling techniques for variable voltage low power designs. ACM Transactions on design Automation of Electronic Systems, 2(2):81- 97, 1997.
13. W. Namgoong, M. Yu, and T. Meng. A high-efficiency variable-voltage CMOS dynamic DC-DC switching regulator. In IEEE International Solid-State Circuits Conference, pages 380-381, 1997.
14. S. Raje and M. Sarrafzadeh. Variable voltage scheduling. In International Symposium on Low Power Design, pages 9-14, 1995.
15. M. Srivastava, A. P. Chandrakasan, and R. W. Brodersen. Predictive system shutdown and other architectural techniques for energy efficient programmable computation. IEEE Transactions on VLSI Systems, 4(1):42-55, 1996.
16. C.-L. Su and A.M. Despain. Cache design trade-offs for power and performance optimization: A case study. In International Symposium on Low Power Design, pages 63-68, 1995.
17. M. Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for reduced CPU energy. In USENIX Symposium on Operating Systems Design and Implementation, pages 13-23, 1994.
18. S.J.E. Wilton and N.P. Jouppi. CACTI: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, 31(5):677-688, 1996.
19. F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced CPU energy. In IEEE Annual Foundations of Computer Science, pages 374-382, 1995.