Reducing transitions on memory buses using sector-based encoding technique

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 190-195

  Aghaghiri, Yazdan ^a   Fallah, Farzan ^b   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY CONSERVATION; INTERCONNECTION NETWORKS; STORAGE ALLOCATION (COMPUTER);

MEMORY BUSES; POWER REDUCTION; SECTOR-BASED ENCODING TECHNIQUE;

CACHE MEMORY;

EID: 0036949789     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146735     Document Type: Conference Paper

References (13)

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