Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading

ACM Transactions on Computer Systems

Volumn 15, Issue 3, 1997, Pages 322-354

  Lo, Jack L ^b   Eggers, Susan J ^b   Emer, Joel S ^c   Levy, Henry M ^b   Stamm, Rebecca L ^c   Tullsen, Dean M ^a,d  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of Washington   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Cache interference; Instruction level parallelism; Measurement; Multiprocessors; Multithreading; Performance; Simultaneous multithreading; Thread level parallelism

Indexed keywords

DESIGN; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; PERFORMANCE;

MULTITHREADING;

COMPUTER SYSTEMS;

EID: 0031199614     PISSN: 07342071     EISSN: None     Source Type: Journal    
DOI: 10.1145/263326.263382     Document Type: Article

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