Cosimulation-based power estimation for system-on-chip design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 3, 2002, Pages 253-265

  Lajolo, Marcello ^a,b   Raghunathan, Anand ^b   Dey, Sujit ^a,c   Lavagno, Luciano ^d  

^a IEEE   (United States)

^b NEC LABORATORIES AMERICA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d UNIVERSITY OF UDINE   (Italy)

Author keywords

Hardware software (HW SW) codesign; Low power design; Power estimation; System on chip (SoC) design

Indexed keywords

COMPUTATION TIME; POWER ESTIMATION; SYSTEM-ON-CHIP DESIGN;

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; ERROR ANALYSIS; ESTIMATION; ITERATIVE METHODS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; STATISTICAL METHODS; SYNCHRONIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036625242     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.1043328     Document Type: Article

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