Power-optimal encoding for a DRAM address bus

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 2, 2002, Pages 109-118

  Cheng, Wei Chung ^a   Pedram, Massoud ^a  

^a University of Southern California ^*  (United States)

Author keywords

Address bus encoding; Bus activity minimization; DRAM power minimization; Time multiplexed bus

Indexed keywords

CODES (SYMBOLS); ELECTRIC POWER SUPPLIES TO APPARATUS; ENCODING (SYMBOLS); INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; SEQUENTIAL SWITCHING;

ADDRESS BUS ENCODING; BUS ACTIVITY MINIMIZATION; POWER MINIMIZATION; PYRAMID CODE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036543204     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.994988     Document Type: Article

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