Instruction buffering to reduce power in processors for signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 5, Issue 4, 1997, Pages 417-424

  Bajwa, Raminder S ^a,b   Hiraki, Mitsuru ^a,c   Kojima, Hirotsugu ^a,c   Gorny, Douglas J ^d   Nitta, Kenichi ^c   Shridhar, Avadhani ^a,b   Seki, Koichi ^a,c   Sasaki, Katsuro ^a,c  

^a IEEE   (United States)

^b HITACHI AMERICA LTD   (United States)

^c HITACHI LTD   (Japan)

^d Silicon Engineering Inc   (United States)

Author keywords

Decoded instruction buffer (DIB); DSP; Instrcution buffering; Low power processors; Multimedia; Signal processing

Indexed keywords

BUFFER STORAGE; DECODING; IMAGE COMPRESSION; INTERACTIVE COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; SPEECH PROCESSING;

DECODED INSTRUCTION BUFFER (DIB);

DIGITAL SIGNAL PROCESSING;

EID: 0031366763     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.645068     Document Type: Article

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