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Volumn Part F129194, Issue , 1999, Pages

Real-Time Task Scheduling for a Variable Voltage Processor

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY UTILIZATION; REAL TIME SYSTEMS;

EID: 84978423018     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isss.1999.814256     Document Type: Conference Paper
Times cited : (60)

References (9)
  • 2
    • 0032311886 scopus 로고    scopus 로고
    • On-line scheduling of hard real-time tasks on variable voltage pro-cessor
    • I. Hong, M. Potkonjak, and M. B. Srivastava. "On-Line Scheduling of Hard Real-Time Tasks on Variable Voltage Pro-cessor". In Proc. of ICCAD-98, pages 653-656, 1998.
    • (1998) Proc. of ICCAD-98 , pp. 653-656
    • Hong, I.1    Potkonjak, M.2    Srivastava, M.B.3
  • 4
    • 0001253255 scopus 로고
    • Optimal sequencing of a single machine subject to precedence constraints
    • E. Lawler. "Optimal Sequencing of a Single Machine Subject to Precedence Constraints". Managements Science, 19, 1973.
    • (1973) Managements Science , vol.19
    • Lawler, E.1
  • 5
    • 84974687699 scopus 로고
    • Scheduling algorithms for multiprogramming in a hard real-time environment
    • C. L. Liu and J. Layland. "Scheduling Algorithms for Multiprogramming in a Hard Real-time Environment". Journal of the ACM, 20(1):46-61, 1973.
    • (1973) Journal of the ACM , vol.20 , Issue.1 , pp. 46-61
    • Liu, C.L.1    Layland, J.2
  • 7
    • 0005032930 scopus 로고    scopus 로고
    • Optimization of supply voltage assignment for power reduction on processor-based sys-tems
    • T. Ishihara and H. Yasuura. "Optimization of Supply Voltage Assignment for Power Reduction on Processor-Based Sys-tems". In Proc. of SASIMI '97, pages 51-58, 1997.
    • (1997) Proc. of SASIMI ' , vol.97 , pp. 51-58
    • Ishihara, T.1    Yasuura, H.2
  • 8
    • 0032157295 scopus 로고    scopus 로고
    • Programmable power management architecture for power reduction
    • September
    • T. Ishihara and H. Yasuura. "Programmable Power Management Architecture for Power Reduction". IEICE Transaction on Electronics, E81-C(9), September 1998.
    • (1998) IEICE Transaction on Electronics , vol.E81-C , Issue.9
    • Ishihara, T.1    Yasuura, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.