Augmenting loop tiling with data alignment for improved cache performance

IEEE Transactions on Computers

Volumn 48, Issue 2, 1999, Pages 142-149

  Panda, Preeti Ranjan ^a,b   Nakamura, Hiroshi ^a,c   Dutt, Nikil D ^a,d   Nicolau, Alexandru ^a,d  

^a IEEE   (United States)

^b SYNOPSYS INC   (United States)

^c UNIVERSITY OF TOKYO   (Japan)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Cache conflict; Data alignment; Data cache; Loop tiling

Indexed keywords

COMPUTER SIMULATION; COMPUTER WORKSTATIONS; DATA ACQUISITION; DATA STRUCTURES; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS);

CACHE CONFLICT; DATA ALIGNMENT TECHNIQUES; LOOP TILING;

BUFFER STORAGE;

EID: 0033076195     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.752655     Document Type: Article

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