메뉴 건너뛰기




Volumn 17, Issue 2, 1998, Pages 96-109

Incorporating DRAM access modes into high-level synthesis

Author keywords

High level synthesis; Memory synthesis

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; OPTIMIZATION; STORAGE ALLOCATION (COMPUTER);

EID: 0032001453     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.681260     Document Type: Article
Times cited : (19)

References (31)
  • 12
    • 85029615262 scopus 로고    scopus 로고
    • in Proc. Eur. Design Test Conf., Paris, France, Mar. 1997, pp. 288-292.
    • P. K. Jha and N. Dutt, "Library mapping for memories," in Proc. Eur. Design Test Conf., Paris, France, Mar. 1997, pp. 288-292.
    • "Library Mapping for Memories,"
    • Jha, P.K.1    Dutt, N.2
  • 30
    • 84976859541 scopus 로고    scopus 로고
    • in Proc. 4th Int. Conf. Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA, Apr. 1991, pp. 63-74.
    • M. Lam, E. Rothberg, and M. E. Wolf, "The cache performance and optimizations of blocked algorithms," in Proc. 4th Int. Conf. Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA, Apr. 1991, pp. 63-74.
    • "The Cache Performance and Optimizations of Blocked Algorithms,"
    • Lam, M.1    Rothberg, E.2    Wolf, M.E.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.