A hierarchical modeling framework for on-chip communication architectures

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 663-670

  Zhu, Xinping ^a   Malik, Sharad ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ON-CHIP BUS SYSTEM; ON-CHIP COMMUNICATION ARCHITECTURE; ON-CHIP PACKET SWITCHING NETWORK; SYSTEM-ON-A CHIP;

CACHE MEMORY; COMPUTATIONAL METHODS; COMPUTER SIMULATION; INTERFACES (COMPUTER); NETWORK PROTOCOLS; OBJECT ORIENTED PROGRAMMING; PACKET SWITCHING; SWITCHING NETWORKS;

LOGIC DESIGN;

EID: 0036911588     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774670     Document Type: Conference Paper

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