A comparison of five different multiprocessor SoC bus architectures

Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001

Volumn , Issue , 2001, Pages 202-209

  Ryu, Kyeong Keol ^a   Shin, Eung ^a   Mooney, V J ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUSES; DECODING; FREQUENCY DIVISION MULTIPLEXING; MULTIPROCESSING SYSTEMS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS; TRANSMITTERS; VIDEO SIGNAL PROCESSING; WIRELESS TELECOMMUNICATION SYSTEMS;

BUS ARCHITECTURE; CROSSBAR SWITCH; MULTI PROCESSOR SYSTEMS; MULTI-PROCESSOR SOC; PROPAGATION DELAYS; SYSTEM ON A CHIP; VIDEO PROCESSING; WIRELESS COMMUNICATIONS;

COMPUTER ARCHITECTURE;

EID: 3042640630     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2001.952283     Document Type: Conference Paper

References (13)

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