Efficient exploration of the SoC communication architecture design space

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 424-430

  Lahiri, Kanishka ^b   Raghunathan, Anand ^a   Dey, Sujit ^b  

^a NEC LABORATORIES AMERICA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; DESIGN; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS; ASYNCHRONOUS TRANSFER MODE; COMMUNICATION CHANNELS (INFORMATION THEORY); NETWORK PROTOCOLS;

COMMUNICATION ARCHITECTURES; DEDICATED CHANNELS; DESIGN SPACE EXPLORATION; HIGH PERFORMANCE SYSTEMS; OPTIMIZATION ALGORITHMS; SOC COMMUNICATIONS; SYSTEM DESIGN FLOWS; SYSTEMATIC EXPLORATION; CENTRAL PROCESSING UNIT; COMMUNICATION ARCHITECTURE; SYSTEM-ON-CHIP;

INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT LAYOUT;

EID: 0034474790     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896509     Document Type: Conference Paper

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