Architectural choices in large scale ATM switches

IEICE Transactions on Communications

Volumn E81-B, Issue 2, 1998, Pages 120-136

  Turner, Jonathan ^a   Yamanaka, Naoaki ^b  

^a WASHINGTON UNIVERSITY IN ST LOUIS   (United States)

^b Nippon Telegraph and Telephone Corporation   (Japan)

Author keywords

Architecture; ATM; B ISDN; Buffer; Switch

Indexed keywords

BROADBAND NETWORKS; BUFFER CIRCUITS; SWITCHING SYSTEMS; SYSTEMS ANALYSIS; VOICE/DATA COMMUNICATION SYSTEMS;

BUFFERED MULTISTAGE SYSTEMS;

ASYNCHRONOUS TRANSFER MODE;

EID: 0031998264     PISSN: 09168516     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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