Power optimization of core-based systems by address bus encoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 4, 1998, Pages 554-562

  Benini, Luca ^b   De Micheli, Giovanni ^a,c   Macii, Enrico ^a,d   Poncino, Massimo ^a,d   Quer, Stefano ^d  

^a IEEE

^b UNIVERSITY OF BOLOGNA   (Italy)

^c STANFORD UNIVERSITY   (United States)

^d POLITECNICO DI TORINO   (Italy)

Author keywords

Bus encoding; Integrated circuit; Intellectual property; Low power; Power optimization

Indexed keywords

DESIGN; ENERGY DISSIPATION; SIGNAL ENCODING;

ADDRESS BUS ENCODING; POWER OPTIMIZATION;

DIGITAL INTEGRATED CIRCUITS;

EID: 0032300757     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.736127     Document Type: Article

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