Wire placement for crosstalk energy minimization in address buses

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 158-162

  Macchiarulo, Luca ^a   Macii, Enrico ^a   Poncino, Massimo ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS BUS; BUS ENERGY; CROSSTALK EFFECT; ENCODING-DECODING; ENERGY MINIMIZATION; NON-UNIFORM SPACING; SIGNAL INTEGRITY;

DESIGN; EXHIBITIONS; WIRE;

CROSSTALK;

EID: 0038453533     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998264     Document Type: Conference Paper

References (9)

1. P. P. Sotiriadis, A. Chandrakasan, "Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep SubMicron Technologies," ICCAD00, pp. 322-327, Nov. 2000.
2. J. Henker, H. Lekatsas, "A2BC: Adaptive Address Bus Coding for Low-Power Deep Sub-Micron Designs," 38th DAC, pp. 744-749, Jun. 2001.
3. K.-W. Kim, K.-H. Baek, N. Shanbag, C.L. Liu, S.-M. Kang, "Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design", ICCAD00, pp. 317-321, Nov. 2000.
4. L. Macchiarulo, E. Macii, M. Poncino, "Low-Energy Encoding for Deep-Submicron Address Buses," ISLPED01, pp. 176-181, Aug. 2001.
5. Y. Shin, T. Sakurai, "Coupling-Driven Bus Design for Low-Power Application-Specific Systems", 38th DAC, pp. 750-753, Jun. 2001.
6. S.P. Khatri, A. Mehrotra, R.K. Brayton, R.H.J.M. Otten, A. Sangiovanni-Vincentelli "A novel VLSI layout fabric for deep submicron applications" 36th DAC, pp. 491-496, Jun. 1999.
7. R. Kumar, "Inerconnect and Noise Immunity Design for the Pentium 4 Processor", Intel Technology Journal Q1, 2001.
8. K. Nahors, J. White, "FastCap: a Multipole Accellerated 3-D Capacitance Extraction Program", IEEE Transactions on CAD, 10(11), pp. 1447-1459, Nov. 1991.
9. G. Servel et al."Inductive Effects on Crosstalk Evaluation", 4th IEEE International Interconnect Technology Conference, San Francisco, Jun. 2001