Vector unit architecture for emotion synthesis

IEEE Micro

Volumn 20, Issue 2, 2000, Pages 40-47

  Kunimatsu, Atsushi ^a,c,d   Ide, Nobuhiro ^a,d,e   Sato, Toshinori ^a   Endo, Yukio ^a,f   Murakami, Hiroaki ^a,g,h   Kamei, Takayuki ^a,c   Hirano, Masashi ^a,i   Ishihara, Fujio ^a,c   Tago, Haruyuki ^a   Oka, Masaaki ^b   Ohba, Akio ^b   Yutaka, Teiji ^b   Okada, Toyoshi ^b   Suzuoki, Masakazu ^b  

^a TOSHIBA CORPORATION   (Japan)

^b Sony Computer Entertainment Inc   (United States)

^c KEIO UNIVERSITY   (Japan)

^d IEEE

^e WASEDA UNIVERSITY   (Japan)

^f UNIVERSITY OF TOKYO   (Japan)

^g Microprocessor Design Department

^h Osaka Prefecture University   (Japan)

ⁱ Ohsawano Technical High School   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EMOTION SYNTHESIS; VECTOR UNITS (VU);

ALGORITHMS; ANIMATION; CMOS INTEGRATED CIRCUITS; COMPUTER SYSTEMS PROGRAMMING; DIGITAL ARITHMETIC; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); THREE DIMENSIONAL COMPUTER GRAPHICS;

COMPUTER ARCHITECTURE;

EID: 12944288247     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.848471     Document Type: Article

References (10)

1. K. Kutaragi et al., "A Microprocessor with 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and MPEG2 Decoder," ISSCC (Int'l Solid-States Circuit Conf.) Digest Tech. Papers, IEEE Press, Piscataway, New Jersey, Feb. 1999, pp. 256-257.
2. F. Michael Raam et al., "A High-Bandwidth Superscalar Microprocessor for Multimedia Applications," ISSCC Digest Tech. Papers, IEEE Press, Feb. 1999, pp. 258-259.
3. A. Kunimatsu et al., "5.5 GFLOPS Vector Units for Emotion Synthesis," Hot Chips 11 Conf. Record, Aug. 1999, pp. 71-82.
4. N. Ide et al., "2.44 GFLOPS 300MHz Floating-Point vector Processing Unit for High-Performance 3D Graphics Computing," Proc. European Solid-State Circuits Conf. (ESSCIRC 99), Editions Frontieres, Gif-sur-Yvette, France, ISBN 2-86332-246-X, 1999. pp. 106-109.
5. M. Oka and M. Suzuoki, "Designing and Programming the Emotion Engine," IEEE Micro, Jan.-Feb 2000, pp. 20-28.
6. Intel Corporation, "Streaming SIMD Extensions Throughput and Latency," Intel(R) Architecture Optimization Reference Manual, 1999, pp. D-1; http://support.intel.com/design/ pentiumiimanuals/245127.htm.
7. H. Tago et al., "Importance of CAD Tools and Methodologies in High Speed CPU Design. "Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC 2000), ACM, New York, Jan. 2000, pp. 631-633.
8. T. Kamei et al., "300MHz Design Methodology of VU for Emotion Synthesis," Proc. ASP-DAC 2000, ACM, Jan. 2000, pp. 635-640.
9. N. Kojima et al., "Repeater Insertion Method and Its Application to the 300MHz 128-Bit 2-Way Superscalar Microprocessor," Proc. ASP-DAC 2000, ACM, Jan. 2000, pp. 641-646.
10. F. Ishihara et al., "Clock Design of 300MHz 128-Bit 2-Way Superscalar Microprocessor," Proc. ASP-DAC 2000, ACM, Jan. 2000, pp. 647-652.