Integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance i-caches

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2001, Pages 147-157

  Yang, Se Hyun ^a   Powell, Michael D ^a   Falsafi, Babak ^a   Roy, Kaushik ^a   Vijaykumar, T N ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; GATES (TRANSISTOR); INTEGRATED CIRCUITS; THRESHOLD VOLTAGE;

EXECUTION TIMES;

BUFFER STORAGE;

EID: 0034825598     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (32)