A partitioning scheme for optimizing interconnect power

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 3, 1997, Pages 433-443

  Mehra, Renu ^a,b,c   Guerra, Lisa M ^a,c,d,e   Rabaey, Jan M ^a,c,f,g  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d STANFORD UNIVERSITY   (United States)

^e Off of Naval Research and AT and T   (Belgium)

^f UNIVERSITY OF LEUVEN   (Belgium)

^g IMEC   (Belgium)

Author keywords

Architecture; Design automation; Interconnect; Low power integrated circuits; Optimization methods; Partitioning; Synthesis

Indexed keywords

ALGORITHMS; AUTOMATION; BUFFER CIRCUITS; CAPACITANCE; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; OPTIMIZATION;

DESIGN AUTOMATION; MULTIPLEXORS; PARTITIONING SCHEME;

ELECTRIC NETWORK SYNTHESIS;

EID: 0031104154     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.557644     Document Type: Article

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