Automatic Architectural Synthesis of VLIW and EPIC Processors

Proceedings of the International Symposium on System Synthesis

Volumn Part F129194, Issue , 1999, Pages

  Aditya, Shail ^a   Ramakrishna Rau, B ^a   Kathail, Vinod ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; INTEGRATED CIRCUIT DESIGN;

ABSTRACT SPECIFICATIONS; ARCHITECTURAL SYNTHESIS; ARCHITECTURE DESIGNS; EXPLICITLY PARALLEL INSTRUCTION COMPUTING; MACHINE DESCRIPTION; PROCESSOR ARCHITECTURES; STRUCTURAL MODELING; VERY LONG INSTRUCTION WORDS;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 16244407568     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isss.1999.814268     Document Type: Conference Paper

References (10)

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2. S. Aditya, B. R. Rau, and R. C. Johnson. Automatic design of VLIW and EPIC instruction formats. Technical Report HPL-1999-94, Hewlett-Packard Laboratories, 1999.
3. G. J. Chaitin. Register allocation and spilling via graph coloring. In Proceedings of the 1982 SIGPLAN Symposium on Compiler Construction, pages 98-105, Boston, Massachusetts, June 23-25, 1982.
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6. th Annual IEEE/ACM Symposium on Microarchitecture (MICRO-29), pages 324-335, Paris, December 1996.
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8. G. Hadjiyiannis, P. Russo, and S. Devadas. A Methodology for Accurate Performance Evaluation in Architecture Exploration. In Design Automation Conference, New Orleans, LA, June 1999.
9. V Kathail, M. Schlansker, and B. R. Rau. HPL PlayDoh architecture specification: Version 1.0. Technical Report HPL-93-80, Hewlett-Packard Laboratories, Feb. 1994.
10. B. R. Rau, V Kathail, and S. Aditya. Machine-description driven compilers for EPIC and VLIW processors. Design Automation for Embedded Systems, 4:71-118, 1999.