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Volumn 5, Issue 4, 1997, Pages 444-455

Low-power encodings for global communication in CMOS VLSI

Author keywords

Global communication in VLSI; Low power encoding; Low power I O; Space encoding; Time encoding; Two dimensional (2 D) codes

Indexed keywords

CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); DATA COMPRESSION; DATA STRUCTURES; INTEGRATED CIRCUIT LAYOUT; REDUNDANCY; SIGNAL ENCODING;

EID: 0031342532     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.645071     Document Type: Article
Times cited : (144)

References (43)
  • 3
    • 85066311525 scopus 로고
    • Low-power techniques for portable real-time DSP application
    • India
    • A. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power techniques for portable real-time DSP application," in VLSI Design, India, 1992.
    • (1992) VLSI Design
    • Chandrakasan, A.1    Sheng, S.2    Brodersen, R.W.3
  • 5
    • 0029192699 scopus 로고
    • Low delay-power product CMOS design using one-hot residue coding
    • Dana Point, CA, Apr.
    • W. A. Chren, "Low delay-power product CMOS design using one-hot residue coding," in Proc. Int. Symp. Low Power Design, Dana Point, CA, Apr. 1995, pp. 145-150.
    • (1995) Proc. Int. Symp. Low Power Design , pp. 145-150
    • Chren, W.A.1
  • 6
    • 0029720341 scopus 로고    scopus 로고
    • Electromigration reliability enhancement via bus activity distribution
    • Las Vegas, NV, June
    • A. Dasgupta and R. Karri, "Electromigration reliability enhancement via bus activity distribution," in Proc. Design Automat. Conf., Las Vegas, NV, June 1996, pp. 353-356.
    • (1996) Proc. Design Automat. Conf. , pp. 353-356
    • Dasgupta, A.1    Karri, R.2
  • 9
    • 33747946662 scopus 로고
    • A 200 mhz, 64 b, dual issue CMOS microprocessor
    • D. Dobberpuhl et al., "A 200 mhz, 64 b, dual issue CMOS microprocessor," in Proc. Int. Solid-State Circuits Conf., 1992, pp. 106-107.
    • (1992) Proc. Int. Solid-State Circuits Conf. , pp. 106-107
    • Dobberpuhl, D.1
  • 10
    • 84866206723 scopus 로고    scopus 로고
    • "Integrated circuit having outputs configured for reduced state changes," U.S. Patent no. 4 667 337, May 1987
    • R. J. Fletcher, "Integrated circuit having outputs configured for reduced state changes," U.S. Patent no. 4 667 337, May 1987.
    • Fletcher, R.J.1
  • 11
    • 0025454898 scopus 로고
    • Error-control coding in computers
    • July
    • E. Fujiwara and D. K. Pradhan, "Error-control coding in computers," Comput., pp. 63-72, July 1990.
    • (1990) Comput. , pp. 63-72
    • Fujiwara, E.1    Pradhan, D.K.2
  • 13
    • 0029191713 scopus 로고
    • Asynchronous design methodologies: An overview
    • Jan.
    • S. Hauck, "Asynchronous design methodologies: An overview," in Proc. IEEE, Jan. 1995, pp. 69-92.
    • (1995) Proc. IEEE , pp. 69-92
    • Hauck, S.1
  • 16
    • 0029194989 scopus 로고
    • Information theoretic measures for energy consumption at register transfer level
    • Dana Point, CA, Apr.
    • D. Marculescu, R. Marculescu, and M. Pedram, "Information theoretic measures for energy consumption at register transfer level," in Proc. Int. Symp. Low Power Design, Dana Point, CA, Apr. 1995, pp. 81-86.
    • (1995) Proc. Int. Symp. Low Power Design , pp. 81-86
    • Marculescu, D.1    Marculescu, R.2    Pedram, M.3
  • 17
    • 0029226463 scopus 로고
    • Efficient power estimation for highly correlated input streams
    • June
    • R. Marculescu, D. Marculescu, and M. Pedram, "Efficient power estimation for highly correlated input streams," in Design Automat. Conf., June 1995, pp. 628-634.
    • (1995) Design Automat. Conf. , pp. 628-634
    • Marculescu, R.1    Marculescu, D.2    Pedram, M.3
  • 18
    • 0038160511 scopus 로고    scopus 로고
    • Algorithm and architectural level methodologies for low power
    • J. M. Rabaey and M. Pedram, Eds. Boston, MA: Kluwer Academic
    • R. Mehra, D. B. Lidsky, A. Abnous, P. E. Landman, and J. M. Rabaey, "Algorithm and architectural level methodologies for low power," in Low Power Design Methodologies, J. M. Rabaey and M. Pedram, Eds. Boston, MA: Kluwer Academic, 1996, pp. 335-362.
    • (1996) Low Power Design Methodologies , pp. 335-362
    • Mehra, R.1    Lidsky, D.B.2    Abnous, A.3    Landman, P.E.4    Rabaey, J.M.5
  • 19
    • 0002774808 scopus 로고
    • Behavioral level power estimation and exploration
    • Napa, CA, Apr.
    • R. Mehra and J. Rabaey, "Behavioral level power estimation and exploration," in Proc. Int. Workshop Low Power Design, Napa, CA, Apr. 1994, pp. 197-202.
    • (1994) Proc. Int. Workshop Low Power Design , pp. 197-202
    • Mehra, R.1    Rabaey, J.2
  • 21
    • 0028135761 scopus 로고
    • A CMOS 160 Mb/s phase modulation I/O interface circuit
    • San Francisco, CA, Feb.
    • K. Nogami and A. El Gamal, "A CMOS 160 Mb/s phase modulation I/O interface circuit," in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 1994, pp. 108-109.
    • (1994) Proc. Int. Solid-State Circuits Conf. , pp. 108-109
    • Nogami, K.1    El Gamal, A.2
  • 22
    • 0001818207 scopus 로고
    • Low-power state assignment for finite state machines
    • Napa, CA, Apr.
    • E. Olson and S. Kang, "Low-power state assignment for finite state machines," in Proc. Int. Workshop Low Power Design, Napa, CA, Apr. 1994, pp. 63-68.
    • (1994) Proc. Int. Workshop Low Power Design , pp. 63-68
    • Olson, E.1    Kang, S.2
  • 23
    • 12344267468 scopus 로고
    • Codes to reduce switching transients across VLSI I/O pins
    • Sept.
    • A. Park and R. Maeder, "Codes to reduce switching transients across VLSI I/O pins," Comput. Arch. News, pp. 17-21, Sept. 1992.
    • (1992) Comput. Arch. News , pp. 17-21
    • Park, A.1    Maeder, R.2
  • 27
    • 0029214569 scopus 로고
    • Application of capacitive coupling to switch fabrics
    • Santa Cruz, CA, Jan.
    • D. Salzmann, T. Knight, and P. Franzon, "Application of capacitive coupling to switch fabrics," in Proc. Multi-Chip Modules Conf., Santa Cruz, CA, Jan. 1995, pp. 195-199.
    • (1995) Proc. Multi-Chip Modules Conf. , pp. 195-199
    • Salzmann, D.1    Knight, T.2    Franzon, P.3
  • 28
    • 0027003872 scopus 로고
    • On average power dissipation and random pattern testability of CMOS combinational logic networks
    • A. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," in Proc. Int. Conf. Computer-Aided Design, Nov. 1992, pp. 402-407.
    • (1992) Proc. Int. Conf. Computer-Aided Design, Nov. , pp. 402-407
    • Shen, A.A.1    Ghosh, A.2    Devadas, S.3    Keutzer, K.4
  • 29
    • 0022118124 scopus 로고
    • Recording codes for digital magnetic storage
    • Sept.
    • P. H. Siegel, "Recording codes for digital magnetic storage," IEEE Trans. Magnet., pp. 1344-1349, Sept. 1985.
    • (1985) IEEE Trans. Magnet. , pp. 1344-1349
    • Siegel, P.H.1
  • 31
    • 33747763131 scopus 로고    scopus 로고
    • Ph.D. dissertation, Univ. Massachusetts, Dep. Elec. Comput. Eng., Sept.
    • M. R. Stan, "Low-power techniques in CMOS VLSI," Ph.D. dissertation, Univ. Massachusetts, Dep. Elec. Comput. Eng., Sept. 1996.
    • (1996) Low-power Techniques in CMOS VLSI
    • Stan, M.R.1
  • 33
    • 35048834531 scopus 로고
    • Bus-invert coding for low power I/O
    • Mar.
    • M. R. Stan and W. P. Burleson, "Bus-invert coding for low power I/O," IEEE Trans. VLSI Syst., vol. 3, pp. 49-58, Mar. 1995.
    • (1995) IEEE Trans. VLSI Syst. , vol.3 , pp. 49-58
    • Stan, M.R.1    Burleson, W.P.2
  • 34
    • 0029229197 scopus 로고
    • Coding a terminated bus for low power
    • Buffalo, NY, Mar.
    • M. R. Stan and W. P. Burleson, "Coding a terminated bus for low power," in Great Lakes Symp. VLSI, Buffalo, NY, Mar. 1995, pp. 70-73.
    • (1995) Great Lakes Symp. VLSI , pp. 70-73
    • Stan, M.R.1    Burleson, W.P.2
  • 37
    • 0028715171 scopus 로고
    • Saving power in the control path of embedded processors
    • C.-L. Su, C.-Y. Tsui, and A. M. Despain, "Saving power in the control path of embedded processors," IEEE Design Test Comput., vol. 11, pp. 24-30, 1994.
    • (1994) IEEE Design Test Comput. , vol.11 , pp. 24-30
    • Su, C.-L.1    Tsui, C.-Y.2    Despain, A.M.3
  • 40
    • 0003400983 scopus 로고
    • N. Weste and K. Eshraghian, Eds., Reading, MA: Addison Wesley
    • N. Weste and K. Eshraghian, Eds., Principles of CMOS VLSI Design. Reading, MA: Addison Wesley, 1993.
    • (1993) Principles of CMOS VLSI Design
  • 42
    • 0029534385 scopus 로고
    • A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-memory
    • Kyoto, Japan, June
    • T. Yamauchi, Y. Morooka, and H. Ozaki, "A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-memory," in Proc. Symp. VLSI Circuits, Kyoto, Japan, June 1995, pp. 27-28.
    • (1995) Proc. Symp. VLSI Circuits , pp. 27-28
    • Yamauchi, T.1    Morooka, Y.2    Ozaki, H.3
  • 43
    • 0017493286 scopus 로고
    • A universal algorithm for sequential data compression
    • J. Ziv and A. Lempel, "A universal algorithm for sequential data compression," IEEE Trans. Inform. Theory, vol. 23, pp. 337-343, 1977.
    • (1977) IEEE Trans. Inform. Theory , vol.23 , pp. 337-343
    • Ziv, J.1    Lempel, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.