Simultaneous reference allocation in code generation for dual data memory bank ASIPs

ACM Transactions on Design Automation of Electronic Systems

Volumn 5, Issue 2, 2000, Pages 242-264

  Sudarsanam, Ashok ^a,b   Malik, Sharad ^a,b  

^a PRINCETON UNIVERSITY   (United States)

^b Princeton University   (United States)

Author keywords

Code generation; Code optimization; Graph labelling; Memory bank assignment; Register allocation

Indexed keywords

EID: 23044519371     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/335043.335047     Document Type: Article

References (28)

1. AHO, A., GANAPATHI, M., AND TJIANG, S. W. K. 1989. Code generation using tree matching and dynamic programming. ACM Trans. Program. Lang. Syst. 11, 4 (Oct. 1989), 491-516.
2. AHO, A., SETHI, R., AND ULLMAN, J. 1986. Compilers: Principles, Techniques, and Tools. Addison-Wesley, Reading, MA.
3. ANDERSON, J. M. AND LAM, M. S. 1993. Global optimizations for parallelism and locality on scalable parallel machines. SIGPLAN Not. 28, G (June 1993), 112-125.
4. ARAUJO, G. AND MALIK, S. 1995. Optimal code generation for embedded memory non-homogeneous register architectures. In Proceedings of the Eighth International Symposium on System Synthesis (Cannes, France, Sept. 13-15, 1995), P. G. Paulin and F. Mavaddat, Eds. ACM Press, New York, NY, 36-41.
5. ARAUJO, G., MALIK, S., AND LEE, M. T.-C. 1996. Using register-transfer paths in code generation for heterogeneous memory-register architectures.' In Proceedings of the 33rd Annual Conference on Design Automation (DAG '96, Las Vegas, NV, June 3-7), T. P. Pennine and E. J. Yoffa, Eds. ACM Press, New York, NY, 591-596.
6. ARAUJO, G., SUDARSANAM, A., AND MALIK, S. 1996. Instruction set design and optimization techniques for address computation in DSP architectures. In Proceedings of the Ninth International Symposium on System Synthesis,
7. CHAITIN, G., AUSLANDER, M., CHANDRA, A., COCKE, J., HOPKINS, M., AND MARKSTEIN, P. 1981. Register allocation via coloring. Comput. Lang. 6, 1, 47-57.
8. FRASER, C. W., HANSON, D. R., AND PROEBSTING, T. A. 1992. Engineering a simple, efficient code-generator generator. ACM Lett. Program. Lang. Syst. l, 3 (Sept. 1992), 213-226.
9. GAREY, M. AND JOHNSON, D. 1979. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman & Co., New York, NY.
10. KAFKA, S. 1990. An assembly source level global compacter for digital signal processors. In Proceedings of the International on Acoustics, Speech, and Signal Processing,
11. KIRKPATRICK, S., GELATT, C. D., JR., AND VECCHI, M. P. 1983. Optimization by simulated annealing. Science 220, 4598 (May), 671-680.
12. LANDSKOV, D., DAVIDSON, S., SHRIVER, B., AND MALLETT, P. 1980. Local microcode compaction techniques. ACM Comput. Surv. 12, 3 (Sept.).
13. LANNEER, D., PRAET, J., SCHOOFS, K., GEURTS, W., THOEN, F., GOOSSENS, G., AND KIFLI, A. 1995. Chess: Retargetable code generation for embedded DSP rocessors. In Code Generation for Embedded Processors, P. Marwedel and J. Goosens, Eds. Kluwer Academic Publishers, Hingham, MA.
14. LEUPERS, R. AND MARWEDEL, P. 1996. Instruction selection for embedded DSPs with complex instructions. In Proceedings of the Conference on European Design Automation (EURO-DAG '96, Geneva, Switzerland, Sept. 16 \), G. Symonds and W. Nebel, Eds. IEEE Computer Society Press, Los Alamitos, CA, 200-205.
15. LEUPERS, R., SCHENK, W., AND MARWEDEL, P. 1994. Retargetable assembly code generation by bootstrapping. In Proceedings of the Seventh International Symposium on High-Level Synthesis (ISSS '94, Niagara-on-the-Lake, Ont., Canada, May 18-20), P. G. Paulin, Ed. IEEE Computer Society Press, Los Alamitos, CA, 88-93.
16. Li, J. AND CHEN, M. 1991. Compiling communication-efficient programs for massively parallel machines. IEEE Trans. Parallel Distrib. Syst. 2, 3 (July), 361-376.
17. LIAO, S., DEVADAS, S., KEUTZER, K., AND TJIANG, S. 1995. Instruction selection using binate covering for code size optimization. In Proceedings of the 1995 IEEE I ACM International Conference on Computer-Aided Design (ICCAD-95, San Jose, CA, Nov. 5-9), R. Rudell, Ed. IEEE Computer Society Press, Los Alamitos, CA, 393-399.
18. LIAO, S., DEVADAS, S., KEUTZER, K., TJIANG, S., AND WANG, A. 1995. Storage assignment to decrease code size. In Proceedings of the Conference on Programming Language Design and Implementation (SIGPLAN '95, La Jolla, CA, June 18-21), D. W. Wall, Ed. ACM Press, New York, NY, 186-195.
19. LIAO, S., DEVADAS, S., KEUTZER, K., TJIANG, S., WANG, A., ARAUJO, G., SUDARSANAM, A., MALIK, S., ZIVOJNOVIC, V., AND MEYR, H. 1996. Code generation and optimization techniques for embedded digital signal processors. In Hardware I Software Co-Design, G. D. Micheli and M. Sami, Eds. Kluwer Academic Publishers, Hingham, MA, 165-186.
20. MOTOROLA 1990. DSP56000/DSP56001 Digital Signal Processor User's Manual. Motorola Inc., Phoenix, AZ.
21. PAULIN, P. G., LIEM, C., MAY, T. C., AND SUTARWALA, S. 1994. CodeSyn: A retargetable.code synthesis system (abstract). In Proceedings of the Seventh International Symposium on High-Level Synthesis (ISSS '94, Niagara-on-the-Lake, Ont., Canada, May 18-20), P. G. Paulin, Ed. IEEE Computer Society Press, Los Alamitos, CA, 94.
22. POWELL, D., LEE, E., AND NEWMAN, W. 1992. Direct synthesis of optimized DSP assembly code from signal flow block diagrams. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing 5, 553-556.
23. SAGHIR, M. A. R., CHOW, P., AND LEE, C. G. 1996. Exploiting dual data-memory banks in digital signal processors. ACM SIGOPS Oper. Syst. Rev. 30, 5, 234-243.
24. SUDARSANAM, A. AND MALIK, S. 1995. Memory bank and register allocation in software synthesis for ASIPs. In Proceedings of the 1995 IEEE I ACM International Conference on Computer-Aided Design (ICCAD-95, San Jose, CA, Nov. 5-9), R. Rudell, Ed. IEEE Computer Society Press, Los Alamitos, CA, 388-392.
25. TEXAS-INSTRUMENTS 1993. TMS320C2x User's Guide. Revision C. Texas Instruments, Austin, TX.
26. WESS, B. 1991. Automatic code generation for integrated digital signal processors. In Proceedings of the 1991 IEEE International Symposium on Circuits and Systems (Singapore, June 11-14), 33-36.
27. WESS, B. 1992. Automatic instruction code generation based on trellis diagrams. In Proceedings of the International Conference on Circuits and Systems, 645-648.
28. ZIVOJNOVIC, V., VELARDE, J. M., AND SCHLäGER, C. 1994. DSPstone: A DSP-oriented benchmarking methodology. In Proceedings of the Fifth International Conference on Signal Processing Applications and Technology (Oct.).