Shared-bus control mechanism and a cache coherence protocol for a high-performance on-chip multiprocessor

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1996, Pages 314-322

  Takahashi, Masafumi ^a   Takano, Hiroyuki ^a   Kaneko, Emi ^a   Suzuki, Seigo ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; DELAY CIRCUITS; MICROCOMPUTERS; MODELS; NETWORK PROTOCOLS; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER); TELECOMMUNICATION TRAFFIC; VLSI CIRCUITS;

CACHE COHERENCE PROTOCOL; CACHE TAGS; CENTRAL COHERENCE UNIT; CLOCK CYCLE; CYCLE BASED MULTIPROCESSOR SIMULATOR; ON CHIP MULTIPROCESSOR; SHARE BUS CONTROL MECHANISM; SHARED BUS TRAFFIC; VLSI TECHNOLOGY;

COMPUTER ARCHITECTURE;

EID: 0029700352     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)