Architectural energy optimization by bus splitting

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 4, 2002, Pages 408-414

  Hsieh, Cheng Ta ^b,c   Pedram, Massoud ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^c Verplex Systems   (United States)

Author keywords

Bus architecture; Energy dissipation model; Low power design

Indexed keywords

BUS ARCHITECTURES;

ALGORITHMS; BANDWIDTH; COMBINATORIAL MATHEMATICS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DATA TRANSFER; ENERGY UTILIZATION; HEURISTIC METHODS; PROBLEM SOLVING;

MICROELECTRONICS;

EID: 0036540701     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.992764     Document Type: Article

References (7)

1. Bus architecture of a system on a chip with user-configurable system logic
2. Sub-1-V swing internal bus architecture for future low-power ULSIs
3. High-level power modeling, estimation and optimization