SCOPUS 정보 검색 플랫폼

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 15-20

LOTTERYBUS: A new high-performance communication architecture for system-on-chip designs

(3) Lahiri, Kanishka a Raghunathan, Anand b Lakshminarayana, Ganesh b

a UNIVERSITY OF CALIFORNIA (United States)

b NEC LABORATORIES AMERICA (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS TRANSFER MODE; BANDWIDTH; COMMUNICATION SYSTEMS; DATA FLOW ANALYSIS; FREQUENCY ALLOCATION; SWITCHING; SYSTEMS ANALYSIS; TELECOMMUNICATION TRAFFIC; TIME DIVISION MULTIPLE ACCESS;

COMMUNICATION ARCHITECTURE; SYSTEM-ON-CHIP (SOC) DESIGNS;

CHIP SCALE PACKAGES;

EID: 0034853719 PISSN: 0738100X EISSN: None Source Type: Journal
DOI: 10.1109/DAC.2001.156100 Document Type: Article

Times cited : (102)

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