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Volumn , Issue , 1998, Pages 297-307
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Precise register allocation for irregular architectures
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Author keywords
[No Author keywords available]
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Indexed keywords
COST EFFECTIVENESS;
INTEGER PROGRAMMING;
MICROPROGRAMMING;
PROGRAM COMPILERS;
RESPONSE TIME (COMPUTER SYSTEMS);
IRREGULAR-REGISTER ARCHITECTURES;
REDUCED INSTRUCTION SET COMPUTING;
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EID: 0032314816
PISSN: 10724451
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (39)
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References (9)
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