Architectural and compiler techniques for energy reduction in high-performance microprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 3, 2000, Pages 317-326

  Bellas, Nikolaos ^b   Hajj, Ibrahim N ^a,c   Polychronopoulos, Constantine D ^c   Stamoulis, George ^d  

^a IEEE

^b MOTOROLA INC   (United States)

^c University of Illinois at Urbana Champaign   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; ELECTRIC LOSSES; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; SWITCHING FUNCTIONS; TRANSISTORS;

CENTRAL PROCESSING UNIT; COMPILER TECHNIQUE; ENERGY REDUCTION; NONNUMERIC NONLOOP INTENSIVE CODE; ON-CHIP CACHE; SIGNAL SWITCHING ACTIVITY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033723926     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.845897     Document Type: Article

References (20)

1. J. Edmondon, "Internal organization of the Alpha 21164, a 300 MHz 64-bit quad-issue CMOS RISC microprocessor," Digital Tech. J., vol. 7, no. 1, pp. 119-135, 1995.
2. D. Dobberpuhl, "The design of a high-performance low-power microprocessor," in Proc. Int. Symp. Low Power Electronics and Design, 1996, pp. 11-16.
3. S. Manne, D. Grunwald, and A. Klauser, "Pipeline gating: Speculation control for energy reduction," in Proc. Int. Symp. Computer Architecture, 1998, pp. 132-141.
4. V. Tiwari, S. Malik, and A. Wolfe, "Power analysis of embedded software: A first step toward software power minimization," IEEE Trans. VLSI Syst., vol. 2, pp. 437-445, Dec. 1994.
5. V. Tiwari, S. Malik, A. Wolfe, and T. C. Lee, "Instruction level power analysis and optimization of software," J. VLSI Signal Processing, vol. 13, Aug. 1996.
6. V. Tiwari, S. Malik, and A. Wolfe, "Compilation techniques for low energy: An overview," in Proc. IEEE Symp. Low Power Electronics, Oct. 1994.
7. H. Mehta, R. M. Owens, M. K. Irwin, R. Chen, and D. Ghosh, "Techniques for low energy software," in Proc. IEEE Symp. Low Power Electronics and Design, Aug. 1997, pp. 72-75.
8. J. Diguet, S. Wuytack, F. Catthoor, and H. De Man, "Formalized methodology for data reuse exploration in hierarchical memory mappings," in Proc. IEEE Symp. Low Power Electronics and Design, Aug. 1997, pp. 30-35.
9. S. Wuytack, F. Catthoor, L. Nachtergaele, and H. De Man, "Power exploration for data dominated video applications," in Proc. IEEE Symp. Low Power Electronics and Design, 1996.
10. J. Kin, M. Gupta, and W. Mangione-Smith, "The filter cache: An energy efficient memory structure," in Proc. IEEE Symp. Micro architecture, Dec. 1997, pp. 184-193.
11. R. Bajwa, M. Hiraki, H. Kojima, D. Gorny, K. Nitta, A. Shridhar, K. Seki, and K. Sasaki, "Instruction buffering to reduce power in processors for signal processing," IEEE Trans. VLSI Syst., vol. 5, pp. 417-424, Dec. 1997.
12. E. Jacobsen, E. Rotenberg, and J. Smith, "Assigning confidence to conditional branch prediction," in Proc. IEEE Symp. Microarchitecture, 1996, pp. 142-152.
13. N. Bellas, I. Hajj, C. Polychronopoulos, and G. Stamoulis, "Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors," in Proc. IEEE Symp. Low Power Electronics and Design, Aug. 1998, pp. 70-75.
14. A. Aho, R. Sethi, and J. Ullman, Compilers: Principles, Techniques and Tools. Reading, MA: Addison-Wesley, 1986.
15. S. McFarling, "Program optimization for instruction caches," in Proc. Int. Conf. Architectural Support for Programming Languages and Operating Systems, June 1989, pp. 16-27.
16. S. Wilson and N. Jouppi, "An enhanced access and cycle time model for on-chip caches," Tech. Rep., DEC WRL 93/5, July 1994.
17. N. Bellas, I. Hajj, and C. Polychropoulos, "A detailed, transistor-level energy model for SRAM-based caches," in Proc. Int. Symp. Circuits and Systems, 1999.
18. J. E. Veenstra and R. J. Fowler, "MINT: A front end for efficient simulation of shared-memory multiprocessors," in Proc. 2nd Int. Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 1994, pp. 201-207.
19. "SpeedShop User's Guide," Silicon Graphics, Inc., 1996.
20. M. Garey and D. Johnson, Computers and Intractability. New York: Freeman, 1979.