Memory-CPU size optimization for embedded system designs

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 246-251

  Shackleford, Barry ^a   Yasuda, Mitsuhiro ^a   Okushi, Etsuko ^a   Koizumi, Hisao ^a   Tomiyama, Hiroyuki ^a   Yasuura, Hiroto ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; ELECTRONIC EQUIPMENT MANUFACTURE; OPTIMIZATION; PROGRAM COMPILERS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING; ROM; SYSTEMS ANALYSIS;

APPLICATION SPECIFIC INTEGRATED PROCESSOR; SYSTEM SPECIFIC PERIPHERAL HARDWARE;

PROGRAM PROCESSORS;

EID: 0030644930     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/266021.266083     Document Type: Conference Paper

References (15)