A chip-multiprocessor architecture with speculative multithreading

IEEE Transactions on Computers

Volumn 48, Issue 9, 1999, Pages 866-880

  Krishnan, Venkata ^a,b   Torrellas, Josep ^c  

^a IEEE   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

Chip multiprocessor; Control speculation; Data dependence speculation; Speculative multithreading

Indexed keywords

BINARY SEQUENCES; BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SUPPORTED COOPERATIVE WORK; NETWORK PROTOCOLS; PARALLEL PROCESSING SYSTEMS;

CHIP MULTIPROCESSOR ARCHITECTURE; CONTROL SPECULATION; DATA DEPENDENCE SPECULATION; SPECULATIVE THREADING;

MICROPROCESSOR CHIPS;

EID: 0033348795     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.795218     Document Type: Article

References (30)

1. W. Blume, R. Doallo, R. Eigenmann, J. Grout, J. Hoeflinger, T. Lawrence, J. Lee, D. Padua, Y. Paek, B. Pottenger, L. Rauchwerger, and P. Tu, "Parallel Programming with Polaris," Computer, vol. 29, no. 12, pp. 78-82, Dec. 1996.
2. S. Breach, T.N. Vijaykumar, and G. Sohi, "The Anatomy of the Register File in a Multiscalar Processor," Proc. 27th Int'l Symp. Microarchitecture (MICRO-27), pp. 181-190, Dec. 1994.
3. R. Colwell and R. Steck, "A 0.6μm BiCMOS Processor with Dynamic Execution," ISSCC Proc., 1995.
4. The 21264: A Superscalar Alpha Processor with Out-of-Order Execution. Microprocessor Forum, Oct. 1996.
5. P. Dubey, K. O'Brien, K. O'Brien, and C. Barton, "Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading," Proc. IFIP WG 10. 3 Working Conf. Parallel Architectures and Compilation Techniques, PACT '95, pp. 109-121, June 1995.
6. M. Fillo, S. Keckler, W. Dally, N. Carter, A. Chang, Y. Gurevich, and W. Lee, "The M-Machine Multicomputer," Proc. 28th Int'l Symp. Computer Microarchitecture (MICRO-28), pp. 146-156, Nov. 1995.
7. M. Franklin and G. Sohi, "ARB: A Hardware Mechanism for Dynamic Memory Disambiguation," IEEE Trans. Computers, vol. 45, no. 5, pp. 552-571, May 1996.
8. S. Gopal, T.N. Vijaykumar, J. Smith, and G. Sohi, "Speculative Versioning Cache," Proc. Fourth Int'l Symp. High-Performance Computer Architecture, pp. 195-205, Feb. 1998.
9. M. Hall, J. Anderson, S. Amarasinghe, B. Murphy, S.-W. Liao, E. Bugnion, and M. Lam, "Maximizing Multiprocessor Performance with the SUIF Compiler," Computer, vol. 29, no. 12, pp. 84-89, Dec. 1996.
10. L. Hammond, B. Nayfeh, and K. Olukotun, "A Single-Chip Multiprocessor," Computer, vol. 30, no. 9, pp. 79-85, Sept. 1997.
11. L. Hammond, M. Willey, and K. Olukotun, "Data Speculation Support for a Chip Multiprocessor," Proc. Eighth Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), Oct. 1998.
12. M. Johnson, Superscalar Microprocessor Design. Prentice Hall, 1990.
13. V. Krishnan and J. Torrellas, "A Direct Execution Framework for Fast and Accurate Simulation of Superscalar Processors," Proc. PACT '98, pp, 286-293, Oct. 1998.
14. V. Krishnan and J. Torrellas, "Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor," Proc. 12th Int'l Conf. Supercomputing (ICS), July 1998.
15. C. Lee, M. Potkonjak, and W. Mangione-Smith, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems," Proc. 30th Int'l Symp. Microarchitecture (MI-CRO-30), pp. 330-335, Dec. 1997.
16. D. Levitan, T. Thomas, and P. Tu, "The PowerPC 620 Microprocessor," Spring CompCon Proc., 1995.
17. P. Marcuello, A. Gonzalez, and J. Tubella, "Speculative Multithreaded Processors," Proc. 12th Int'l Conf. Supercomputing (ICS), July 1998.
18. D. Matzke, "Will Physical Scalability Sabotage Performance Gains?" Computer, vol. 30, no. 9, pp. 37-39, Sept. 1997.
19. MIPS Technologies, Inc., R10000 Microprocessor Chipset, Product Overview, 1994.
20. A. Moshovos, S. Breach, T.N. Vijaykumar, and G. Sohi, "Dynamic Speculation and Synchronization of Data Dependences," Proc. 24th Int'l Symp. Computer Architecture, pp. 181-193, June 1997.
21. J. Oplinger, D. Heine, S.-W. Liao, B. Nayfeh, M. Lam, and K. Olukotun, "Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor," Technical Report CSL-TR-97-715, Computer Systems Laboratory, Stanford Univ., Feb. 1997.
22. S. Palacharla, N. Jouppi, and J. Smith, "Complexity-Effective Superscalar Processors," Proc. 24th Int'l Symp. Computer Architecture, pp. 206-218, June 1997.
23. E. Rotenberg, S. Bennett, and J. Smith, "Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching," Proc. 29th Int'l Symp. Microarchitecture (MICRO-29), pp. 24-34, Dec. 1996.
24. E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith, "Trace Processors," Proc. 30th Int'l Symp. Microarchitecture (MICRO-30), pp. 138-148, Dec. 1997.
25. J. Smith and S. Vajapeyam, "Trace Processors: Moving to Fourth Generation Microarchitectures," Computer, vol. 30, no. 9, pp. 68-74, Sept. 1997.
26. G. Sohi, S. Breach, and T.N. Vijaykumar, "Multiscalar Processors," Proc. 22nd Int'l Symp. Computer Architecture, pp. 414-425, June 1995.
27. J. Steffan and T. Mowry, "The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization," Proc. Fourth Int'l Symp. High-Performance Computer Architecture, pp. 2-13 Feb. 1998.
28. J. Tsai and P. Yew, "The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation," Proc. PACT '96, pp. 35-46, Oct. 1996.
29. J. Veenstra and R. Fowler, "MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors," Proc. MASCOTS '94, pp. 201-207, Jan. 1994.
30. T.N. Vijaykumar and G. Sohi, "Task Selection for a Multiscalar Processor," Proc. 31st Int'l Symp. Microarchitecture (MICRO-31), Dec. 1998.