Power-aware partitioned cache architectures

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 64-67

  Kim, S ^a   Vijaykrishnan, N ^a   Kandemir, M ^a   Sivasubramaniam, A ^a   Irwin, M J ^a   Geethanjali, E ^a  

^a The Center for Nanotechnology Education and Utilization   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; DATA HANDLING; DELAY CIRCUITS; ENERGY EFFICIENCY;

SUB CACHE ARCHITECTURES;

CACHE MEMORY;

EID: 0034875609     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383095     Document Type: Conference Paper

References (10)

1. Selective cache ways: On-demand cache resource allocation
2. Multiple-banked register file architecture
3. A data cache with multiple caching strategies tuned for different types of locality
4. Way-predicting set-associative cache for high performance and low energy consumption
5. Run-time adaptive cache hierarchy management via reference analysis
6. Analytical energy dissipation models for low power caches
7. An enhanced access and cycle time model for on-chip caches