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Volumn , Issue , 1996, Pages 67-77
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Evaluation of design alternatives for a multiprocessor microprocessor
a
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Author keywords
[No Author keywords available]
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Indexed keywords
BUFFER STORAGE;
COMPUTER HARDWARE;
COMPUTER OPERATING SYSTEMS;
COMPUTER SIMULATION;
MICROCOMPUTERS;
MICROPROCESSOR CHIPS;
MULTIPROCESSING SYSTEMS;
MULTIPROGRAMMING;
PARALLEL PROCESSING SYSTEMS;
PROGRAM COMPILERS;
RESPONSE TIME (COMPUTER SYSTEMS);
STORAGE ALLOCATION (COMPUTER);
COMPUTER ARCHITECTURE;
INTEGRATED CIRCUIT LAYOUT;
MATHEMATICAL MODELS;
CPU;
INPUT OUTPUT DEVICES;
INTERPROCESSOR COMMUNICATION;
MEMORY HIERARCHY;
MULTIPROCESSOR MICROPROCESSOR;
SHARED MEMORY;
SHARED PRIMARY CACHE;
SHARED SECONDARY CACHE;
COMPUTER ARCHITECTURE;
MICROPROCESSOR CHIPS;
MULTIPROCESSOR MICROPROCESSORS;
SHARED MEMORY ARCHITECTURE;
SHARED PRIMARY CACHE ARCHITECTURE;
SHARED SECONDARY CACHE ARCHITECTURE;
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EID: 0029666647
PISSN: 08847495
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/232973.232982 Document Type: Conference Paper |
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Times cited : (48)
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References (27)
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