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Volumn 18, Issue 2, 2000, Pages 217-247

Timing analysis for instruction caches

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SYSTEMS PROGRAMMING; DATA FLOW ANALYSIS; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

EID: 0033732401     PISSN: 09226443     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008145215849     Document Type: Article
Times cited : (131)

References (33)
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    • Li, Y.-T.S.1    Malik, S.2    Wolfe, A.3
  • 18
    • 0030414718 scopus 로고    scopus 로고
    • Cache modeling for real-time software: Beyond direct mapped instruction caches
    • December
    • Li, Y.-T. S., Malik, S., and Wolfe, A. December 1996. Cache modeling for real-time software: Beyond direct mapped instruction caches. IEEE Real-Time Systems Symposium: 254-263.
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    • January
    • Liu, C., and Layland, J. January 1973. Scheduling algorithms for multiprogramming in a hard-real-time environment. J. of the Association for Computing Machinery 20(1): 46-61.
    • (1973) J. of the Association for Computing Machinery , vol.20 , Issue.1 , pp. 46-61
    • Liu, C.1    Layland, J.2
  • 23
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    • Generalizing timing predictions to set-associative caches
    • June
    • Mueller, F. June 1997. Generalizing timing predictions to set-associative caches. EuroMicro Workshop on Real-Time Systems: 64-71.
    • (1997) EuroMicro Workshop on Real-Time Systems , pp. 64-71
    • Mueller, F.1
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    • March
    • Park, C. Y. March 1993. Predicting program execution times by analyzing static and dynamic program paths. Real-Time Systems 5(1): 31-61.
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  • 27
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    • December PhD thesis, Dept. of CS, Technical University Vienna
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.