POWER4 system microarchitecture

IBM Journal of Research and Development

Volumn 46, Issue 1, 2002, Pages 5-25

  Tendler, Joel M ^a   Dodson, J Steve ^a   Fields Jr , J S ^a   Le, Hung ^a   Sinharoy, Balaram ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; LITHOGRAPHY; SERVERS; SYSTEMS ENGINEERING; UNIX;

PROCESSOR MICROARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 0036298603     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.461.0005     Document Type: Article

References (21)

1. The IBM RISC system/6000 processor hardware overview
2. The evolution of RISC technology at IBM
3. POWER2: Next generation of the RISC system/6000 family
4. Design considerations for the powerPC 601 microprocessor
5. POWER3: Next generation 64-bit powerPC processor design
6. 4th generation 64-bit powerPC- compatible commercial processor design
7. 5th generation 64-bit powerPC-compatible commercial processor design
8. A multithreaded powerPC processor for commercial servers
9. POWER3: The next generation of powerPC processors
10. High-performance 0.18 μm SOI CMOS technology
11. Speed kills
12. Fault-tolerant design of the IBM pseries 690 system using POWER4 processor technology
13. The circuit and physical design of the POWER4 microprocessor
14. A comparison of dynamic branch predictors that use two levels of branch history
15. The alpha 21264 microprocessor
16. Target prediction for indirect jumps
17. Subroutine call/return stack
18. POWER4 synchronous wave-pipelined interface