Assigning program and data objects to scratchpad for energy reduction

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 409-416

  Steinke, Stefan ^a   Wehmeyer, Lars ^a   Lee, Bo Sik ^a   Marwedel, Peter ^a  

^a TU DORTMUND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BATTERY CAPACITY; ENERGY EFFICIENT; ENERGY REDUCTION; HARDWARE CONTROL; MEMORY ACCESS; MOBILE APPLICATIONS; SCRATCH PAD MEMORY; SOFTWARE CONTROL;

APPLICATION PROGRAMS; DESIGN; ENERGY EFFICIENCY; ENERGY UTILIZATION; EXHIBITIONS; PROGRAM COMPILERS;

CACHE MEMORY;

EID: 84893786147     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998306     Document Type: Conference Paper

References (21)

1. ARM. Advanced RISC Machines Ltd. www.arm.com.
2. R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel. Comparison of cache-and scratch-pad-based memory systems with respect to performance, area and energy consumption. Technical Report 762, University of Dortmund, Sep. 2001.
3. L. Benini, A. Macii, E. Macii, and M. Ponicino. Synthesis of application-specific memories for power optimization in embedded systems. In Proc. of the 37th Design Automation Conference, pages 300-303, Los Angeles, CA, Jun. 2000.
4. encc. University of Dortmund, Computer Science Dep., ls12-www.cs.uni- dortmund.de/research/encc.
5. Intel. Mobile Power Guidelines 2000. Technical Report 1.0, Intel Corporation, Dec. 1998.
6. T. Ishihara and H. Yasuura. A power reduction technique with object code merging for application specific embedded processors. In Proc. of the Design, Automation and Test in Europe Conference, pages 617-623, Paris, France, Mar. 2000.
7. M. Kandemir, J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif, and A. Parikh. Dynamic Management of Scratch-Pad Memory Space. In Proc. of 38th Design Automation Conference, pages 690-695, Las Vegas, NV, Jun. 2001.
8. M. Kandemir, I. M. Vijakrishnan N., and W. Ye. Influence of compiler optimizations on system power. In Proc. of the 37th Design Automation Conference, pages 304-307, Los Angeles, CA, Jun. 2000.
9. G. L. Nehmhauser and L. A. Wolsey. Integer and Combinatorial Optimization. John Wilsey and Sons, New York, NY, 1988.
10. P. R. Panda, N. D. Dutt, and A. Nicolau. Efficient utilization of scratch-pad memory in embedded processor applications. In Proc. of European Design and Test Conference, Paris, France, Mar. 1997.
11. P. R. Panda, N. D. Dutt, and A. Nicolau. Memory Issues in Embedded Systems-On-Chip. Kluwer Academic Publishers, Norwell, MA, 1999.
12. R. Sedgewick. Algorithms. Addison Wesley, Massachusetts, 1988.
13. T. Simunic, L. Benini, and G. De Micheli. Cycle-accurate simulation of energy consumption in embedded systems. In Proc. of the 36th Design Automation Conference, pages 867-872, New Orleans, LA, Jun. 1999.
14. J. Sjödin, B. Fröderberg, and T. Lindgren. Allocation of Global Data Objects in On-Chip RAM. In Proc. Workshop on Compiler and Architectural Support for Embedded Computer Systems, Washington DC, Dec. 1998. ACM.
15. S. Steinke, M. Knauer, L. Wehmeyer, and P. Marwedel. An accurate and fine grain instruction-level energy model supporting software optimizations. In PATMOS 01, Yverdon-Les-Bains, Switzerland, Sep. 2001.
16. Synopsys. Power Products Reference Manual V3.5. synopsys, 1996.
17. V. Tiwari. Logic and System Design for Low Power Consumption. PhD Thesis, Princeton University, Princeton, NJ, 1996.
18. V. Tiwari, S. Malik, and A. Wolfe. Compilation techniques for low energy: An overview. In Proceedings of the IEEE Symposium on Low Power Electronics, San Diego, CA, Oct. 1994.
19. V. Tiwari, S. Malik, and A. Wolfe. Instruction level power analysis and optimization of software. Journal of VLSI Signal Processing Systems, Aug. 1996.
20. S. J. E. Wilton and N. P. Jouppi. An Enhanced Access and Cycle Time Model for On-Chip Caches. Technical Report 93/5, Western Research Laboratory, Jul. 1994.
21. S. J. E.Wilton and N. P. Jouppi. CACTI: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, 31(5):677-688, May 1996.