Tolerating Latency in Multiprocessors through Compiler-Inserted Prefetching

ACM Transactions on Computer Systems

Volumn 16, Issue 1, 1998, Pages 55-92

  Mowry, Todd C ^a  

^a Carnegie Mellon University   (United States)

Author keywords

B.3.2 Memory Structures : Design Styles cache memories; Compiler optimization; D.3.4 Programming Languages : Processors compilers; Design; Experimentation; Optimization; Performance; Prefetching

Indexed keywords

ALGORITHMS; BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; FAULT TOLERANT COMPUTER SYSTEMS; MULTIPROCESSING SYSTEMS; OPTIMIZATION; PROGRAM PROCESSORS;

COMPILER INSERTED PREFETCHING; TOLERATING LATENCY;

PROGRAM COMPILERS;

EID: 0031988272     PISSN: 07342071     EISSN: None     Source Type: Journal    
DOI: 10.1145/273011.273021     Document Type: Article

References (43)

1. ABU-SUFAH, W., KUCK, D. J., AND LAWRIE, D. H. 1979. Automatic program transformations for virtual memory computers. In Proceedings of the 1979 National Computer Conference. 969-974.
2. ADVE, S. AND HILL, M. 1990. Weak ordering - A new definition. In Proceedings of the 17th Annual International Symposium on Computer Architecture (May). 2-14.
3. AMARASINGHE, S. P. AND LAM, M. S. 1993. Communication optimization and code generation for distributed memory machines. In Proceedings of the SIGPLAN '93 Conference on Programming Language Design and Implementation (June). 126-138.
4. ANDERSON, J. M. AND LAM, M. S. 1993. Global optimizations for parallelism and locality on scalable parallel machines. In Proceedings of the SIGPLAN '93 Conference on Programming Language Design and Implementation (June). ACM, New York, 112-125.
5. BAER, J.-L. AND CHEN, T.-F. 1991. An effective on-chip preloading scheme to reduce data access penalty. In Proceedings of Supercomputing '91.
6. CALLAHAN, D. AND PORTERFIELD, A. 1990. Data cache performance of supercomputer applications. In Proceedings of Supercomputing '90. 564-572.
7. CALLAHAN, D., KENNEDY, K., AND PORTERFIELD, A. 1991. Software prefetching. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems (April). ACM, New York, 40-52.
8. COLWELL, R. P., NIX, R. P., O'DONNELL, J. J., PAPWORTH, D. B., AND RODMAN, P. K. 1987. A vliw architecture for a trace scheduling compiler. In Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems (Oct.). ACM, New York, 180-192.
9. CONVEX COMPUTER. 1994. Convex Exemplar Architecture. Convex Computer Corp.
10. COOPER, K., HALL, M., AND KENNEDY, K. 1993. A methodology for procedure cloning. Comput. Lang. 19, 2 (April).
11. DEHNERT, J. C., Hsu, P. Y.-T., AND BRATT, J. P. 1989. Overlapped loop support in the cydra 5. In Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS III) (April). ACM, New York, 26-38.
12. DUBOIS, M., SCHEURICH, C., AND BRIGGS, F. A. 1988. Synchronization, coherence, and event ordering in multiprocessors. Computer 21, 2 (Feb.), 9-21.
13. EGGERS, S. J. AND JEREMIASSEN, T. E. 1991. Eliminating false sharing. In Proceedings of the 1991 International Conference on Parallel Processing. Vol. 1 (Aug.). 377-381.
14. GALLIVAN, K., JALBY, W., MEIER, U., AND SAMEH, A. 1987. The impact of hierarchical memory systems on linear algebra algorithm design. Tech. Rep. UIUCSRD 625, Univ. of Illinois, Urbana-Champaign, Ill.
15. GANNON, D. AND JALBY, W. 1987. The influence of memory hierarchy on algorithm organization: Programming FFTs on a vector multiprocessor. In The Characteristics of Parallel Algorithms. MIT Press, Cambridge, Mass.
16. GHARACHORLOO, K., GUPTA, A., AND HENNESSY, J. 1991. Performance evaluation of memory consistency models for shared-memory multiprocessors. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems (April). ACM, New York, 245-257.
17. GHARACHORLOO, K., LENOSKI, D., LAUDON, J., GIBBONS, P., GUPTA, A., AND HENNESSY, J. 1990. Memory consistency and event ordering in scalable shared-memory multiprocessors. In Proceedings of the 17th Annual International Symposium on Computer Architecture (May). 15-26.
18. GOLDSCHMIDT, S. R. AND DAVIS, H. 1990. Tango introduction and tutorial. Tech. Rep. CSL-TR-90-410, Stanford Univ., Palo Alto, Calif.
19. GOLUB, G. H. AND LOAN, C. F. V. 1989. Matrix Computations. Johns Hopkins University Press, Baltimore, Md.
20. GORNISH, E., GRANSTON, E., AND VEIDENBAUM, A. 1990. Compiler-directed data prefetching in multiprocessors with memory hierarchies. In Proceedings of the International Conference on Supercomputing.
21. GORNISH, E. H. 1989. Compile time analysis for data prefetching. Master's thesis, Univ. of Illinois, Urbana-Champaign, Ill.
22. GUPTA, A., HENNESSY, J., GHARACHORLOO, K., MOWRY, T., AND WEBER, W.-D. 1991. Comparative evaluation of latency reducing and tolerating techniques. In Proceedings of the 18th Annual International Symposium on Computer Architecture (May). 254-263.
23. KLAIBER, A. C. AND LEVY, H. M. 1991. Architecture for software-controlled data prefetching. In Proceedings of the 18th Annual International Symposium on Computer Architecture (May). 43-63.
24. KONTOTHANASSIS, L., SUGUMAR, R., FAANES, G., SMITH, J., AND SCOTT, M. 1994. Cache performance in vector supercomputers. In Proceedings of Supercomputing '94. 255-264.
25. KROFT, D. 1981. Lockup-free instruction fetch/prefetch cache organization. In Proceedings of the 8th Annual International Symposium on Computer Architecture. 81-85.
26. LAMPORT, L. 1979. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Comput. C-28, 9 (Sept.), 241-248.
27. LAUDON, J. AND LENOSKI, D. 1997. The SGI Origin: A ccNUMA highly scalable server. In Proceedings of the 24th International Symposium on Computer Architecture (June). 241-251.
28. LEE, R. L. 1987. The effectiveness of caches and data prefetch buffers in large-scale shared memory multiprocessors. Ph.D. thesis, Dept. of Computer Science, Univ. of Illinois, Urbana-Champaign, Ill.
29. LENOSKI, D., GHARACHORLOO, K., LAUDON, J., GUPTA, A., HENNESSY, J., HOROWITZ, M., AND LAM, M. 1992. The Stanford DASH multiprocessor. IEEE Comput. 25, 3 (Mar.), 63-79.
30. LUK, C.-K. AND MOWRY, T. C. 1996. Compiler-based prefetching for recursive data structures. In Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (Oct.). ACM, New York, 222-233.
31. LUSK, E., OVERBEEK, R., ET AL. 1987. Portable Programs for Parallel Processors. Holt, Rinehart and Winston, Inc.
32. MCKELLER, A. C. AND COFFMAN, E. G. 1969. The organization of matrices and matrix operations in a paged multiprogramming environment. Commun. ACM 12, 3, 153-165.
33. MOWRY, T. AND GUPTA, A. 1991. Tolerating latency through software-controlled prefetching in shared-memory multiprocessors. J. Parallel Distrib. Comput. 12, 2, 87-106.
34. MOWRY, T. C. 1994. Tolerating latency through software-controlled data prefetching. Ph.D. thesis, Stanford Univ., Palo Alto, Calif.
35. MOWRY, T. C., LAM, M. S., AND GUPTA, A. 1992. Design and evaluation of a compiler algorithm for prefetching. In Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems. Vol. 27 (Oct.). 62-73.
36. PORTERFIELD, A. K. 1989. Software methods for improvement of cache performance on supercomputer applications. Ph.D. thesis, Dept. of Computer Science, Rice Univ., Houston, Tex.
37. SINGH, J. P., WEBER, W.-D., AND GUPTA, A. 1991. Splash: Stanford parallel applications for shared memory. Tech. Rep. CSL-TR-91-469, Stanford Univ., Palo Alto, Calif.
38. STENSTROM, P. 1990. A survey of cache coherence schemes for multiprocessors. IEEE Comput. 23, 6 (June), 12-24.
39. TJIANG, S. W. K. AND HENNESSY, J. L. 1992. Sharlit: A tool for building optimizers. In Proceedings of the SIGPLAN Conference on Programming Language Design and Implementation. ACM, New York.
40. TORRELLAS, J., LAM, M. S., AND HENNESSY, J. L. 1990. Shared data placement optimizations to reduce multiprocessor cache miss rates. In Proceedings of the 1990 International Conference on Parallel Processing. Vol. 2 (Aug.). 266-270.
41. TULLSEN, D. M. AND EGGERS, S. J. 1993. Limitations of cache prefetching on a bus-based multiprocessor. In Proceedings of the 20th Annual International Symposium on Computer Architecture (May). 278-288.
42. WEBER, W.-D. 1993. Scalable directories for cache-coherent shared-memory multiprocessors. Ph.D. thesis, Stanford Univ., Palo Alto, Calif.
43. WOLF, M. E. AND LAM, M. S. 1991. A data locality optimizing algorithm. In Proceedings of the SIGPLAN '91 Conference on Programming Language Design and Implementation (June). ACM, New York, 30-44.