Communication architecture tuners: A methodology for the design of high-performance communication architectures for system-on-chips

Proceedings-Design Automation Conference

Volumn , Issue , 2000, Pages 513-518

  Lahiri, Kanishka ^a   Raghunathan, Anand ^b   Lakshminarayana, Ganesh ^b   Dey, Sujit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ASYNCHRONOUS TRANSFER MODE; COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PACKET NETWORKS; QUEUEING NETWORKS;

COMMUNICATION ARCHITECTURE TUNERS; SYSTEMS ON CHIPS;

NETWORK PROTOCOLS;

EID: 0033685462     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855364     Document Type: Article

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