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Volumn , Issue , 2012, Pages 275-282

Progress and challenges in VLSI placement research

Author keywords

[No Author keywords available]

Indexed keywords

VLSI CIRCUITS;

EID: 84872296473     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2429384.2429441     Document Type: Conference Paper
Times cited : (46)

References (179)
  • 1
    • 29144472522 scopus 로고    scopus 로고
    • Combinatorial techniques for mixed-size placement
    • S. N. Adya, I. L. Markov, "Combinatorial Techniques for Mixed-size Placement", TODAES 10(1) 2005, pp. 58-90.
    • (2005) TODAES , vol.10 , Issue.1 , pp. 58-90
    • Adya, S.N.1    Markov, I.L.2
  • 2
    • 33646496133 scopus 로고    scopus 로고
    • On whitespace and stability in physical synthesis
    • S. N. Adya, I. L. Markov, P. G. Villarrubia, "On Whitespace and Stability in Physical Synthesis", Integration 39(4) 2006, pp. 340-362.
    • (2006) Integration , vol.39 , Issue.4 , pp. 340-362
    • Adya, S.N.1    Markov, I.L.2    Villarrubia, P.G.3
  • 4
    • 43349096114 scopus 로고    scopus 로고
    • Techniques for fast physical synthesis
    • C. J. Alpert et al., "Techniques for Fast Physical Synthesis", IEEE 95(3) 2007,pp. 573-599.
    • (2007) IEEE , vol.95 , Issue.3 , pp. 573-599
    • Alpert, C.J.1
  • 5
    • 0038040192 scopus 로고    scopus 로고
    • Porosity aware buffered steiner tree construction
    • C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, S. T. Quay, "Porosity Aware Buffered Steiner Tree Construction", ISPD 2003, pp. 158-165.
    • (2003) ISPD , pp. 158-165
    • Alpert, C.J.1    Gandham, G.2    Hrkic, M.3    Hu, J.4    Quay, S.T.5
  • 9
    • 84862104585 scopus 로고    scopus 로고
    • VLSI legalization with minimum perturbation by iterative augmentation
    • U. Brenner, "VLSI Legalization with Minimum Perturbation by Iterative Augmentation", DATE 2012 pp. 1385-1390.
    • (2012) DATE , pp. 1385-1390
    • Brenner, U.1
  • 10
    • 0036375967 scopus 로고    scopus 로고
    • An effective congestion driven placement framework
    • U. Brenner, A. Rohe, "An Effective Congestion Driven Placement Framework", ISPD 2002, pp. 6-11.
    • (2002) ISPD , pp. 6-11
    • Brenner, U.1    Rohe, A.2
  • 11
    • 54549117207 scopus 로고    scopus 로고
    • Faster optimal single-row placement with fixed ordering
    • U. Brenner, J. Vygen, "Faster Optimal Single-row Placement with Fixed Ordering", DATE 2000, pp. 117-121.
    • (2000) DATE , pp. 117-121
    • Brenner, U.1    Vygen, J.2
  • 12
    • 10044270827 scopus 로고    scopus 로고
    • Legalizing a Placement with Minimum Total Movement
    • U. Brenner, J.Vygen,"Legalizing a Placement with Minimum Total Movement", TCAD 23(12) 2004, pp.1597-1613.
    • (2004) TCAD , vol.23 , Issue.12 , pp. 1597-1613
    • Brenner, U.1    Vygen, J.2
  • 13
    • 50549085604 scopus 로고    scopus 로고
    • BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms
    • U. Brenner, M. Struzyna, J. Vygen, "BonnPlace: Placement of Leading-edge Chips by Advanced Combinatorial Algorithms", TCAD 27(9) 2008, pp.1607-1620.
    • (2008) TCAD , vol.27 , Issue.9 , pp. 1607-1620
    • Brenner, U.1    Struzyna, M.2    Vygen, J.3
  • 15
    • 0022228071 scopus 로고
    • Timing influenced layout design
    • M. Burstein, M. N. Youssef, "Timing Influenced Layout Design", DAC 1985, pp. 124-130.
    • (1985) DAC , pp. 124-130
    • Burstein, M.1    Youssef, M.N.2
  • 16
    • 0032595815 scopus 로고    scopus 로고
    • On wirelength estimations for row-based placement
    • A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, A. Zelikovsky, "On Wirelength Estimations for Row-based Placement", TCAD 18(9) 1999, pp. 1265-1278.
    • (1999) TCAD , vol.18 , Issue.9 , pp. 1265-1278
    • Caldwell, A.E.1    Kahng, A.B.2    Mantik, S.3    Markov, I.L.4    Zelikovsky, A.5
  • 17
    • 0033697586 scopus 로고    scopus 로고
    • Can recursive bisection alone produce routable placements?
    • A. E. Caldwell, A. B. Kahng, I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?" DAC 2000, pp. 477-482.
    • (2000) DAC , pp. 477-482
    • Caldwell, A.E.1    Kahng, A.B.2    Markov, I.L.3
  • 18
    • 0034313430 scopus 로고    scopus 로고
    • Optimal partitioners and end-case placers for standard-cell layout
    • A. E. Caldwell, A. B. Kahng, I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout", TCAD 19(11) 2000, pp. 1304-1313.
    • (2000) TCAD , vol.19 , Issue.11 , pp. 1304-1313
    • Caldwell, A.E.1    Kahng, A.B.2    Markov, I.L.3
  • 19
    • 79953848782 scopus 로고    scopus 로고
    • A parallel branch-and-cut approach for detailed placement
    • 18
    • S. Cauley, V. Balakrishnan, Y. C. Hu, C.-K. Koh, "A Parallel Branch-and-Cut Approach for Detailed Placement", TODAES 16(2) 2011, no. 18.
    • (2011) TODAES , vol.16 , Issue.2
    • Cauley, S.1    Balakrishnan, V.2    Hu, Y.C.3    Koh, C.-K.4
  • 20
    • 29144468974 scopus 로고    scopus 로고
    • Multilevel generalized force-directed method for circuit placement
    • T. F. Chan, J. Cong, K. Sze, "Multilevel Generalized Force-directed Method for Circuit Placement", ISPD 2005, pp. 185-192.
    • (2005) ISPD , pp. 185-192
    • Chan, T.F.1    Cong, J.2    Sze, K.3
  • 22
    • 76349088035 scopus 로고    scopus 로고
    • A rigorous framework for convergent net weighting schemes in timing-driven placement
    • T. F. Chan, J. Cong, E. Radke, "A Rigorous Framework for Convergent Net Weighting Schemes in Timing-driven Placement", ICCAD 2009, pp. 288-294.
    • (2009) ICCAD , pp. 288-294
    • Chan, T.F.1    Cong, J.2    Radke, E.3
  • 23
    • 78650883034 scopus 로고    scopus 로고
    • Post-placement power optimization with multi-bit flip-flops
    • Y.-T. Chang, C.-C. Hsu, M. P.-H. Lin, Y.-W. Tsi, S.-F. Chen, "Post-placement Power Optimization with Multi-bit Flip-flops", ICCAD 2010, pp. 218-223.
    • (2010) ICCAD , pp. 218-223
    • Chang, Y.-T.1    Hsu, C.-C.2    Lin, M.P.-H.3    Tsi, Y.-W.4    Chen, S.-F.5
  • 24
    • 0036374222 scopus 로고    scopus 로고
    • Net criticality revisited: An effective method to improve timing in physical design
    • H. Chang, E. Shragowitz, J. Liu, H. Youssef, B. Lu, S. Sutanthavibul, "Net Criticality Revisited: An Effective Method to Improve Timing in Physical Design", ISPD 2002, pp. 155-160.
    • (2002) ISPD , pp. 155-160
    • Chang, H.1    Shragowitz, E.2    Liu, J.3    Youssef, H.4    Lu, B.5    Sutanthavibul, S.6
  • 25
    • 84954416950 scopus 로고    scopus 로고
    • Multi-level placement for large-scale mixed-size IC design
    • C. Chang, J. Cong, X. Yuan, "Multi-level Placement for Large-scale Mixed-size IC Design", ASPDAC 2003, pp. 325-330.
    • (2003) ASPDAC , pp. 325-330
    • Chang, C.1    Cong, J.2    Yuan, X.3
  • 26
    • 57849099197 scopus 로고    scopus 로고
    • Constraint graph-based macro placement for modern mixed-size circuit designs
    • H.-C. Chen, Y.-L. Chuang, Y.-W. Chang, Y.-C. Chang, "Constraint Graph-based Macro Placement for Modern Mixed-size Circuit Designs", ICCAD 2008, pp. 218-223.
    • (2008) ICCAD , pp. 218-223
    • Chen, H.-C.1    Chuang, Y.-L.2    Chang, Y.-W.3    Chang, Y.-C.4
  • 27
    • 51549090631 scopus 로고    scopus 로고
    • An integrated nonlinear placement framework with congestion and porosity aware buffer planning
    • T.-C. Chen, A. Chakraborty, D. Z. Pan, "An Integrated Nonlinear Placement Framework with Congestion and Porosity Aware Buffer Planning", DAC 2008, pp. 702-707.
    • (2008) DAC , pp. 702-707
    • Chen, T.-C.1    Chakraborty, A.2    Pan, D.Z.3
  • 28
    • 56749109565 scopus 로고    scopus 로고
    • Metal-density-driven placement for CMP variation and routability
    • T.-C. Chen, M. Cho, D. Z. Pan, Y.-W. Chang, "Metal-density-driven Placement for CMP Variation and Routability", TCAD 27(12) 2008, pp. 2145-2155.
    • (2008) TCAD , vol.27 , Issue.12 , pp. 2145-2155
    • Chen, T.-C.1    Cho, M.2    Pan, D.Z.3    Chang, Y.-W.4
  • 29
    • 50549094673 scopus 로고    scopus 로고
    • MP-trees: A packing-based macro placement algorithm for modern mixed-size designs
    • T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, T.-Y. Liu, "MP-Trees: A Packing-based Macro Placement Algorithm for Modern Mixed-size Designs", TCAD 27(9) 2008, pp. 1621-1634.
    • (2008) TCAD , vol.27 , Issue.9 , pp. 1621-1634
    • Chen, T.-C.1    Yuh, P.-H.2    Chang, Y.-W.3    Huang, F.-J.4    Liu, T.-Y.5
  • 30
    • 0002097074 scopus 로고
    • RISA: Accurate and efficient placement routability modeling
    • C. E. Cheng, "RISA: Accurate and Efficient Placement Routability Modeling", ICCAD 1994, pp. 650-695.
    • (1994) ICCAD , pp. 650-695
    • Cheng, C.E.1
  • 31
    • 45849140142 scopus 로고    scopus 로고
    • NTUPlace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints
    • T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, Y.-W. Chang, "NTUPlace3: An Analytical Placer for Large-scale Mixed-size Designs with Preplaced Blocks and Density Constraints", TCAD 27(7) 2008, pp.1228-1240.
    • (2008) TCAD , vol.27 , Issue.7 , pp. 1228-1240
    • Chen, T.-C.1    Jiang, Z.-W.2    Hsu, T.-C.3    Chen, H.-C.4    Chang, Y.-W.5
  • 33
    • 70350062055 scopus 로고    scopus 로고
    • Register placement for high-performance circuits
    • M.-F. Chiang, T. Okamoto, T. Yoshimura, "Register Placement for High-performance Circuits", DATE 2009, pp. 1470-1475.
    • (2009) DATE , pp. 1470-1475
    • Chiang, M.-F.1    Okamoto, T.2    Yoshimura, T.3
  • 34
    • 77956221573 scopus 로고    scopus 로고
    • History-based VLSI legalization using network flow
    • M. Cho, H. Ren, H. Xiang, R. Puri, "History-based VLSI Legalization using Network Flow", DAC 2010, pp. 286-291.
    • (2010) DAC , pp. 286-291
    • Cho, M.1    Ren, H.2    Xiang, H.3    Puri, R.4
  • 35
    • 84872317029 scopus 로고    scopus 로고
    • Hierarchical global floorplacement using simulated annealing and network flow area migration
    • W. Choi, K. Bazargan, "Hierarchical Global Floorplacement using Simulated Annealing and Network Flow Area Migration",DATE 2003,pp. 1104-5.
    • (2003) DATE , pp. 1104-1105
    • Choi, W.1    Bazargan, K.2
  • 36
    • 84863537357 scopus 로고    scopus 로고
    • Structure-aware placement for datapath-intensive circuit designs
    • S. Chou, M.-K. Hsu, Y.-W. Chang, "Structure-aware Placement for Datapath-intensive Circuit Designs", DAC 2012, pp. 762-767.
    • (2012) DAC , pp. 762-767
    • Chou, S.1    Hsu, M.-K.2    Chang, Y.-W.3
  • 37
    • 27944476056 scopus 로고    scopus 로고
    • How accurately can we model timing in a placement engine
    • A. Chowdhary et al., "How Accurately Can We Model Timing in a Placement Engine", DAC 2005, pp. 801-806.
    • (2005) DAC , pp. 801-806
    • Chowdhary, A.1
  • 38
    • 34547267305 scopus 로고    scopus 로고
    • IPR: An integrated placement and routing algorithm
    • C. Chu, M. Pan, "IPR: An Integrated Placement and Routing Algorithm", DAC 2007, pp. 59-62.
    • (2007) DAC , pp. 59-62
    • Chu, C.1    Pan, M.2
  • 39
    • 84862908140 scopus 로고    scopus 로고
    • PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs
    • Y.-L. Chuang, H.-T. Lin, T.-Y. Ho, Y.-W. Chang, D. Marculescu, "PRICE: Power Reduction by Placement and Clock-network Co-synthesis for Pulsed-latch Designs", ICCAD 2011, pp. 85-90.
    • (2011) ICCAD , pp. 85-90
    • Chuang, Y.-L.1    Lin, H.-T.2    Ho, T.-Y.3    Chang, Y.-W.4    Marculescu, D.5
  • 41
    • 84860231365 scopus 로고    scopus 로고
    • Towards layout-friendly high-level synthesis
    • J. Cong, B. Liu, G. Luo, R. Prabhakar, "Towards Layout-friendly High-level Synthesis", ISPD 2012, pp. 165-172.
    • (2012) ISPD , pp. 165-172
    • Cong, J.1    Liu, B.2    Luo, G.3    Prabhakar, R.4
  • 42
    • 56749087820 scopus 로고    scopus 로고
    • Highly efficient gradient computation for density-constrained analytical placement
    • J. Cong, G. Luo, E. Radke, "Highly Efficient Gradient Computation for Density-constrained Analytical Placement",TCAD 27(12) 2008,pp.2133-44.
    • (2008) TCAD , vol.27 , Issue.12 , pp. 2133-2144
    • Cong, J.1    Luo, G.2    Radke, E.3
  • 43
  • 44
    • 33745968360 scopus 로고    scopus 로고
    • A robust detailed placement for mixed-size IC designs
    • J. Cong, M. Xie, "A Robust Detailed Placement for Mixed-size IC Designs", ASPDAC 2006, pp. 188-194.
    • (2006) ASPDAC , pp. 188-194
    • Cong, J.1    Xie, M.2
  • 45
    • 33748626715 scopus 로고    scopus 로고
    • Robust mixed-size placement under tight white-space constraints
    • J. Cong, M. Romesis, J. R. Shinnerl, "Robust Mixed-size Placement Under Tight White-space Constraints", ICCAD 2005, pp. 165-172.
    • (2005) ICCAD , pp. 165-172
    • Cong, J.1    Romesis, M.2    Shinnerl, J.R.3
  • 46
    • 76349116045 scopus 로고    scopus 로고
    • GRPlacer: Improving routability and wirelength of global routing with circuit replacement
    • K.-R. Dai, C.-H. Lu, Y.-L. Li, "GRPlacer: Improving Routability and Wirelength of Global Routing with Circuit Replacement", ICCAD 2009, pp. 351-356.
    • (2009) ICCAD , pp. 351-356
    • Dai, K.-R.1    Lu, C.-H.2    Li, Y.-L.3
  • 47
    • 0028516550 scopus 로고
    • Iterative placement improvement by network flow methods
    • K. Doll, F. M. Johannes, K. J. Antreich, "Iterative Placement Improvement by Network Flow Methods", TCAD 13(10) 1994, pp. 1189-1200.
    • (1994) TCAD , vol.13 , Issue.10 , pp. 1189-1200
    • Doll, K.1    Johannes, F.M.2    Antreich, K.J.3
  • 50
    • 0031632293 scopus 로고    scopus 로고
    • Generic global placement and floorplanning
    • H. Eisenmann, F. M. Johannes, "Generic Global Placement and Floorplanning", DAC 1998, pp. 269-274.
    • (1998) DAC , pp. 269-274
    • Eisenmann, H.1    Johannes, F.M.2
  • 51
    • 0026984773 scopus 로고
    • A performance driven macro-cell placement algorithm
    • T. Gao, P. M. Vaidya, C. L. Liu, "A Performance Driven Macro-cell Placement Algorithm", DAC 1992, pp. 147-152.
    • (1992) DAC , pp. 147-152
    • Gao, T.1    Vaidya, P.M.2    Liu, C.L.3
  • 53
    • 0033701024 scopus 로고    scopus 로고
    • A sensitivity based placer for standard cells
    • B. Halpin, C. Y. R. Chen, N. Sehgal, "A Sensitivity Based Placer for Standard Cells", GSLVLSI, 2000, pp. 193-196.
    • (2000) GSLVLSI , pp. 193-196
    • Halpin, B.1    Chen, C.Y.R.2    Sehgal, N.3
  • 54
    • 0034841992 scopus 로고    scopus 로고
    • Timing driven placement using physical net constraints
    • B. Halpin, C. Y. R. Chen, N. Sehgal, "Timing Driven Placement using Physical Net Constraints", DAC 2001, pp. 780-783.
    • (2001) DAC , pp. 780-783
    • Halpin, B.1    Chen, C.Y.R.2    Sehgal, N.3
  • 55
    • 84872332616 scopus 로고    scopus 로고
    • Detailed placement with net length constraints
    • B. Halpin, C. Y. R. Chen, N. Sehgal, "Detailed Placement with Net Length Constraints", IWSOC 2003, pp. 22-27.
    • (2003) IWSOC , pp. 22-27
    • Halpin, B.1    Chen, C.Y.R.2    Sehgal, N.3
  • 56
    • 0027316516 scopus 로고
    • Prime: A timing-driven placement tool using a piecewise linear resistive network approach
    • T. Hamada, C. K. Cheng, P. M. Chau, "Prime: A Timing-driven Placement Tool using a Piecewise Linear Resistive Network Approach", DAC 1993, pp. 531-536, 1993.
    • (1993) DAC , vol.1993 , pp. 531-536
    • Hamada, T.1    Cheng, C.K.2    Chau, P.M.3
  • 57
    • 0023568910 scopus 로고
    • Circuit placement for predictable performance
    • P. S. Hauge, R. Nair, E. J. Yoffa, "Circuit Placement for Predictable Performance", ICCAD 1987, pp. 88-91.
    • (1987) ICCAD , pp. 88-91
    • Hauge, P.S.1    Nair, R.2    Yoffa, E.J.3
  • 58
    • 84863393886 scopus 로고    scopus 로고
    • Ripple: An effective routability-driven placer by iterative cell movement
    • X. He, T. Huang, L. Xiao, H. Tian, G. Cui, E. F. Young, "Ripple: An Effective Routability-driven Placer by Iterative Cell Movement", ICCAD 2011, pp. 74-79.
    • (2011) ICCAD , pp. 74-79
    • He, X.1    Huang, T.2    Xiao, L.3    Tian, H.4    Cui, G.5    Young, E.F.6
  • 60
    • 78650937558 scopus 로고    scopus 로고
    • Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization
    • T.-Y. Ho, S.-H. Liu, "Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization", VLSI-SoC 2010, pp. 369-374.
    • (2010) VLSI-SoC , pp. 369-374
    • Ho, T.-Y.1    Liu, S.-H.2
  • 61
    • 84949799169 scopus 로고    scopus 로고
    • A new congestion-driven placement algorithm based on cell inflation
    • W. Hou, H. Yu, X. Hong, Y. Cai, W. Wu, J. Gu, W. H. Kao, "A New Congestion-driven Placement Algorithm Based on Cell Inflation", ASPDAC 2001, pp. 723-728.
    • (2001) ASPDAC , pp. 723-728
    • Hou, W.1    Yu, H.2    Hong, X.3    Cai, Y.4    Wu, W.5    Gu, J.6    Kao, W.H.7
  • 62
    • 78650921590 scopus 로고    scopus 로고
    • Unified analytical global placement for large-scale mixed-size circuit designs
    • M.-K. Hsu, Y.-W. Chang, "Unified Analytical Global Placement for Large-scale Mixed-size Circuit Designs", ICCAD 2010, pp. 657-662.
    • (2010) ICCAD , pp. 657-662
    • Hsu, M.-K.1    Chang, Y.-W.2
  • 63
    • 80052663262 scopus 로고    scopus 로고
    • TSV-aware analytical placement for 3D IC designs
    • M.-K. Hsu, Y.-W. Chang, V. Balabanov, "TSV-aware Analytical Placement for 3D IC Designs", DAC 2011, pp. 664-669.
    • (2011) DAC , pp. 664-669
    • Hsu, M.-K.1    Chang, Y.-W.2    Balabanov, V.3
  • 64
    • 84862907542 scopus 로고    scopus 로고
    • Routability-driven analytical placement for mixed-size circuit designs
    • M.-K. Hsu, S. Chou, T.-H. Lin, Y.-W. Chang, "Routability-driven Analytical Placement for Mixed-size Circuit Designs", ICCAD 2011, pp. 80-84.
    • (2011) ICCAD , pp. 80-84
    • Hsu, M.-K.1    Chou, S.2    Lin, T.-H.3    Chang, Y.-W.4
  • 65
    • 0036907181 scopus 로고    scopus 로고
    • Congestion minimization during placement without estimation
    • B. Hu, M. Marek-Sadowska, "Congestion Minimization during Placement without Estimation", ICCAD 2002, pp. 739-745.
    • (2002) ICCAD , pp. 739-745
    • Hu, B.1    Marek-Sadowska, M.2
  • 66
    • 23744469942 scopus 로고    scopus 로고
    • Multilevel fixed-point-addition-based VLSI placement
    • B. Hu, M. Marek-Sadowska, "Multilevel Fixed-point-addition-based VLSI Placement", TCAD 24(8) 2005, pp. 1188-1203.
    • (2005) TCAD , vol.24 , Issue.8 , pp. 1188-1203
    • Hu, B.1    Marek-Sadowska, M.2
  • 67
    • 84872316960 scopus 로고    scopus 로고
    • Sensitivity-guided metaheuristics for accurate discrete gate sizing
    • J. Hu, A. B. Kahng, S.-H. Kang, M.-C. Kim, I. L. Markov, "Sensitivity-guided Metaheuristics for Accurate Discrete Gate Sizing", ICCAD 2012.
    • (2012) ICCAD
    • Hu, J.1    Kahng, A.B.2    Kang, S.-H.3    Kim, M.-C.4    Markov, I.L.5
  • 68
    • 16244400467 scopus 로고    scopus 로고
    • Architecting voltage islands in core-based system-on - A-chip designs
    • J. Hu, Y. Shin, N. Dhanwada, R. Marculescu, "Architecting Voltage Islands in Core-based System-on-a-Chip Designs", ISLPED 2004, pp. 180-5.
    • (2004) ISLPED , pp. 180-185
    • Hu, J.1    Shin, Y.2    Dhanwada, N.3    Marculescu, R.4
  • 69
    • 77952285597 scopus 로고    scopus 로고
    • Completing high-quality routes
    • J. Hu, J. A. Roy, I. L. Markov, "Completing High-quality Routes", ISPD 2010, pp. 35-41.
    • (2010) ISPD , pp. 35-41
    • Hu, J.1    Roy, J.A.2    Markov, I.L.3
  • 70
  • 72
    • 0034478056 scopus 로고    scopus 로고
    • Mongrel: Hybrid techniques for standard cell placement
    • S.-W. Hur, J. Lillis, "Mongrel: Hybrid Techniques for Standard Cell Placement", ICCAD 2000, pp. 165-170
    • (2000) ICCAD , pp. 165-170
    • Hur, S.-W.1    Lillis, J.2
  • 73
    • 84872308501 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors (ITRS)
    • International Technology Roadmap for Semiconductors (ITRS). http://public.itrs.net
  • 74
    • 0024911063 scopus 로고
    • Performance-driven placement of cell based ICS
    • M. A. B. Jackson, E. S. Kuh, "Performance-driven Placement of Cell Based ICs", DAC 1989, pp. 370-375.
    • (1989) DAC , pp. 370-375
    • Jackson, M.A.B.1    Kuh, E.S.2
  • 75
    • 33846239297 scopus 로고    scopus 로고
    • RBI: Simultaneous placement and routing optimization technique
    • D. Jariwala, J. Lillis, "RBI: Simultaneous Placement and Routing Optimization Technique", TCAD 26(1) 2007, pp. 127-141.
    • (2007) TCAD , vol.26 , Issue.1 , pp. 127-141
    • Jariwala, D.1    Lillis, J.2
  • 76
    • 51549118747 scopus 로고    scopus 로고
    • Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs
    • Z.-W. Jiang, B.-Y. Su, Y.-W. Chang, "Routability-driven Analytical Placement by Net Overlapping Removal for Large-scale Mixed-size Designs", DAC 2008, pp. 167-172.
    • (2008) DAC , pp. 167-172
    • Jiang, Z.-W.1    Su, B.-Y.2    Chang, Y.-W.3
  • 77
    • 84863033814 scopus 로고    scopus 로고
    • INTEGRA: Fast multibit flip-flop clustering for clock power saving
    • H.-R. Jiang, C.-L. Chang, Y.-M. Yang, "INTEGRA: Fast Multibit Flip-flop Clustering for Clock Power Saving", TCAD 31(2) 2012, pp. 192-204.
    • (2012) TCAD , vol.31 , Issue.2 , pp. 192-204
    • Jiang, H.-R.1    Chang, C.-L.2    Yang, Y.-M.3
  • 78
    • 0033705078 scopus 로고    scopus 로고
    • Classical floorplanning harmful?
    • A. B. Kahng, "Classical Floorplanning Harmful?" ISPD 2000, pp. 207-213.
    • (2000) ISPD , pp. 207-213
    • Kahng, A.B.1
  • 80
    • 2942676623 scopus 로고    scopus 로고
    • On legalization of row-based placements
    • A. B. Kahng, I. L. Markov, S. Reda, "On Legalization of Row-based Placements", GSLVLSI, 2004, pp. 214-219.
    • (2004) GSLVLSI , pp. 214-219
    • Kahng, A.B.1    Markov, I.L.2    Reda, S.3
  • 81
    • 60349130059 scopus 로고    scopus 로고
    • Lens aberration aware placement for timing yield
    • 16
    • A. B. Kahng, C.-H. Park, P. Sharma, Q. Wang, "Lens Aberration Aware Placement for Timing Yield", TODAES 14(1) 2009, no. 16.
    • (2009) TODAES , vol.14 , Issue.1
    • Kahng, A.B.1    Park, C.-H.2    Sharma, P.3    Wang, Q.4
  • 82
    • 2942673331 scopus 로고    scopus 로고
    • Optimization of linear placements for wirelength minimization with free sites
    • A. B. Kahng, P. Tucker, A. Zelikovsky, "Optimization of Linear Placements for Wirelength Minimization with Free Sites",ASPDAC 1999,pp. 241-4.
    • (1999) ASPDAC , pp. 241-244
    • Kahng, A.B.1    Tucker, P.2    Zelikovsky, A.3
  • 83
    • 33745945864 scopus 로고    scopus 로고
    • A faster implementation of APlace
    • A. B. Kahng, Q. Wang, "A Faster Implementation of APlace", ISPD 2006, pp. 218-220.
    • (2006) ISPD , pp. 218-220
    • Kahng, A.B.1    Wang, Q.2
  • 84
    • 84856433796 scopus 로고    scopus 로고
    • Assembling 2-D blocks into 3-d chips
    • J. Knechtel, I. L. Markov, J. Lienig, "Assembling 2-D Blocks Into 3-D Chips", TCAD 31(2) 2012, pp. 228-241.
    • (2012) TCAD , vol.31 , Issue.2 , pp. 228-241
    • Knechtel, J.1    Markov, I.L.2    Lienig, J.3
  • 85
    • 78650896423 scopus 로고    scopus 로고
    • SimPL: An effective placement algorithm
    • M.-C. Kim, D.-J. Lee, I. L. Markov, "SimPL: An Effective Placement Algorithm", ICCAD 2010, pp. 649-656.
    • (2010) ICCAD , pp. 649-656
    • Kim, M.-C.1    Lee, D.-J.2    Markov, I.L.3
  • 86
    • 84862908296 scopus 로고    scopus 로고
    • A SimPLR method for routability-driven placement
    • M.-C. Kim, J. Hu, D.-J. Lee, I. L. Markov, "A SimPLR Method for Routability-driven Placement", ICCAD 2011, pp. 67-73.
    • (2011) ICCAD , pp. 67-73
    • Kim, M.-C.1    Hu, J.2    Lee, D.-J.3    Markov, I.L.4
  • 87
    • 84255204462 scopus 로고    scopus 로고
    • SimPL: An effective placement algorithm
    • M.-C. Kim, D.-J. Lee, I. L. Markov, "SimPL: An Effective Placement Algorithm", TCAD 31(1) 2012, pp.50-60.
    • (2012) TCAD , vol.31 , Issue.1 , pp. 50-60
    • Kim, M.-C.1    Lee, D.-J.2    Markov, I.L.3
  • 88
    • 84863548619 scopus 로고    scopus 로고
    • ComPLx: A competitive primal-dual lagrange optimization for global placement
    • M.-C. Kim, I. L. Markov, "ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement", DAC 2012, pp. 747-752.
    • (2012) DAC , pp. 747-752
    • Kim, M.-C.1    Markov, I.L.2
  • 89
    • 84860233072 scopus 로고    scopus 로고
    • MAPLE: Multilevel adaptive placement for mixed-size designs
    • M.-C. Kim, N. Viswanathan, C. J. Alpert, I. L. Markov, S. Ramji, "MAPLE: Multilevel Adaptive PLacEment for Mixed-size Designs", ISPD 2012, pp. 193-200.
    • (2012) ISPD , pp. 193-200
    • Kim, M.-C.1    Viswanathan, N.2    Alpert, C.J.3    Markov, I.L.4    Ramji, S.5
  • 90
    • 0036907067 scopus 로고    scopus 로고
    • A novel net weighting algorithm for timing-driven placement
    • T. Kong, "A Novel Net Weighting Algorithm for Timing-driven Placement", ICCAD 2002, pp. 172-176.
    • (2002) ICCAD , pp. 172-176
    • Kong, T.1
  • 91
    • 0036911921 scopus 로고    scopus 로고
    • Managing power and performance for system-on-chip designs using voltage islands
    • D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D. W. Stout, S. W. Gould and J. M. Cohn, "Managing Power and Performance for System-on-Chip Designs using Voltage Islands", ICCAD 2002, pp. 195-202.
    • (2002) ICCAD , pp. 195-202
    • Lackey, D.E.1    Zuchowski, P.S.2    Bednar, T.R.3    Stout, D.W.4    Gould, S.W.5    Cohn, J.M.6
  • 92
    • 84863011686 scopus 로고    scopus 로고
    • Obstacle-aware clock-tree shaping during placement
    • D.-J. Lee, I. L. Markov, "Obstacle-aware Clock-tree Shaping during Placement", TCAD 31(2) 2012, pp. 205-216.
    • (2012) TCAD , vol.31 , Issue.2 , pp. 205-216
    • Lee, D.-J.1    Markov, I.L.2
  • 93
    • 77951230474 scopus 로고    scopus 로고
    • A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance
    • Y.-M. Lee, T.-Y. Wu, P.-Y. Chang, "A Hierarchical Bin-based Legalizer for Standard-cell Designs with Minimal Disturbance", ASPDAC 2010, pp. 568-573.
    • (2010) ASPDAC , pp. 568-573
    • Lee, Y.-M.1    Wu, T.-Y.2    Chang, P.-Y.3
  • 94
    • 34548124869 scopus 로고    scopus 로고
    • Recursive function smoothing of half-perimeter wirelength for analytical placement
    • C. Li, C.-K. Koh, "Recursive Function Smoothing of Half-perimeter Wirelength for Analytical Placement", ISQED, 2007, pp. 829-834.
    • (2007) ISQED , pp. 829-834
    • Li, C.1    Koh, C.-K.2
  • 95
    • 29144440605 scopus 로고    scopus 로고
    • Floorplan management: Incremental placement for gate sizing and buffer insertion
    • C. Li, C.-K. Koh, P. H. Madden, "Floorplan Management: Incremental Placement for Gate Sizing and Buffer Insertion",ASPDAC 2005,pp. 349-54.
    • (2005) ASPDAC , pp. 349-354
    • Li, C.1    Koh, C.-K.2    Madden, P.H.3
  • 96
    • 34248524608 scopus 로고    scopus 로고
    • Routability-driven placement and white space allocation
    • C. Li, M. Xie, C.-K. Koh, J. Cong, P. H. Madden, "Routability-driven Placement and White Space Allocation", TCAD 26(5) 2007, pp. 858-871.
    • (2007) TCAD , vol.26 , Issue.5 , pp. 858-871
    • Li, C.1    Xie, M.2    Koh, C.-K.3    Cong, J.4    Madden, P.H.5
  • 97
    • 84860257488 scopus 로고    scopus 로고
    • Mixed integer programming models for detailed placement
    • S. Li, C.-K. Koh, "Mixed Integer Programming Models for Detailed Placement", ISPD 2012, pp. 87-94.
    • (2012) ISPD , pp. 87-94
    • Li, S.1    Koh, C.-K.2
  • 98
    • 79952149496 scopus 로고    scopus 로고
    • Making fast buffer insertion even faster via approximation techniques
    • Z. Li, C. N. Sze, C. J. Alpert, J. Hu, W. Shi, "Making Fast Buffer Insertion Even Faster via Approximation Techniques", ASPDAC 2005, pp. 13-18.
    • (2005) ASPDAC , pp. 13-18
    • Li, Z.1    Sze, C.N.2    Alpert, C.J.3    Hu, J.4    Shi, W.5
  • 99
    • 29844454164 scopus 로고    scopus 로고
    • Congestion driven incremental placement algorithm for standard cell layout
    • Z. Li, W. Wu, X. Hong, "Congestion Driven Incremental Placement Algorithm for Standard Cell Layout", ASPDAC 2003, pp. 723-728.
    • (2003) ASPDAC , pp. 723-728
    • Li, Z.1    Wu, W.2    Hong, X.3
  • 100
    • 33748593901 scopus 로고    scopus 로고
    • Power driven placement with layout aware supply voltage assignment for voltage island generation in dual-vdd designs
    • B. Liu, Y. Cai, Q. Zhou, X. Hong, "Power Driven Placement with Layout Aware Supply Voltage Assignment for Voltage Island Generation in Dual-Vdd Designs", ASPDAC 2006, pp. 582-587.
    • (2006) ASPDAC , pp. 582-587
    • Liu, B.1    Cai, Y.2    Zhou, Q.3    Hong, X.4
  • 101
    • 0026175521 scopus 로고
    • A fast physical constraint generator for timing driven placement
    • W. K. Luk, "A Fast Physical Constraint Generator for Timing Driven Placement", DAC 1991, pp. 626-631.
    • (1991) DAC , pp. 626-631
    • Luk, W.K.1
  • 102
    • 34547154837 scopus 로고    scopus 로고
    • A new LP based incremental timing driven placement for high performance designs
    • T. Luo, D. Newmark, D. Z. Pan, "A New LP Based Incremental Timing Driven Placement for High Performance Designs", DAC 2006, pp. 1115-20.
    • (2006) DAC , pp. 1115-1120
    • Luo, T.1    Newmark, D.2    Pan, D.Z.3
  • 103
    • 49549110217 scopus 로고    scopus 로고
    • DPlace2.0: A stable and efficient analytical placement based on diffusion
    • T. Luo, D. Z. Pan, "DPlace2.0: A Stable and Efficient Analytical Placement Based on Diffusion", ASPDAC 2008, pp. 346-351.
    • (2008) ASPDAC , pp. 346-351
    • Luo, T.1    Pan, D.Z.2
  • 104
    • 33751414789 scopus 로고    scopus 로고
    • Computational geometry based placement migration
    • T. Luo, H. Ren, C. J. Alpert, D. Z. Pan, "Computational Geometry Based Placement Migration", DAC 2007, pp. 41-47.
    • (2007) DAC , pp. 41-47
    • Luo, T.1    Ren, H.2    Alpert, C.J.3    Pan, D.Z.4
  • 105
    • 27944447299 scopus 로고    scopus 로고
    • Navigating registers in placement for clock network minimization
    • Y. Lu, C. N. Sze, X. Hong, Q. Zhou, Y. Cai, L. Huang, J. Hu, "Navigating Registers in Placement for Clock Network Minimization", DAC 2005, pp. 176-181.
    • (2005) DAC , pp. 176-181
    • Lu, Y.1    Sze, C.N.2    Hong, X.3    Zhou, Q.4    Cai, Y.5    Huang, L.6    Hu, J.7
  • 106
    • 16244422171 scopus 로고    scopus 로고
    • Interconnect-power dissipation in a microprocessor
    • N. Magen, A. Kolodny, U. Weiser, N. Shamir, "Interconnect-power Dissipation in a Microprocessor", SLIP 2004, pp. 7-13.
    • (2004) SLIP , pp. 7-13
    • Magen, N.1    Kolodny, A.2    Weiser, U.3    Shamir, N.4
  • 108
    • 0024716080 scopus 로고
    • Generation of performance constraints for layout
    • R. Nair, C. L. Berman, P. S. Hauge, E. J. Yoffa, "Generation of Performance Constraints for Layout", TCAD 8(8) 1989, pp. 860-874.
    • (1989) TCAD , vol.8 , Issue.8 , pp. 860-874
    • Nair, R.1    Berman, C.L.2    Hauge, P.S.3    Yoffa, E.J.4
  • 110
    • 2442504820 scopus 로고    scopus 로고
    • Temperature-aware global placement
    • B. Obermeier, F. M. Johannes, "Temperature-aware Global Placement", ASPDAC 2004, pp. 143-148.
    • (2004) ASPDAC , pp. 143-148
    • Obermeier, B.1    Johannes, F.M.2
  • 111
    • 29144504040 scopus 로고    scopus 로고
    • Kraftwerk: A versatile placement approach
    • B. Obermeier, H. Ranke, F. M. Johannes, "Kraftwerk: a Versatile Placement Approach", ISPD 2005, pp. 242-244.
    • (2005) ISPD , pp. 242-244
    • Obermeier, B.1    Ranke, H.2    Johannes, F.M.3
  • 113
    • 84860237262 scopus 로고    scopus 로고
    • The ISPD-2012 discrete cell sizing contest and benchmark suite
    • M. M. Ozdal, C. Amin, A. Ayupov, S. Burns, G. Wilke, C. Zhuo, "The ISPD-2012 Discrete Cell Sizing Contest and Benchmark Suite", ISPD 2012, pp. 161-164.
    • (2012) ISPD , pp. 161-164
    • Ozdal, M.M.1    Amin, C.2    Ayupov, A.3    Burns, S.4    Wilke, G.5    Zhuo, C.6
  • 114
    • 46149111721 scopus 로고    scopus 로고
    • FastRoute: A step to integrate global routing into placement
    • M. Pan, C. Chu, "FastRoute: A Step to Integrate Global Routing into Placement", ICCAD 2006, pp. 59-62.
    • (2006) ICCAD , pp. 59-62
    • Pan, M.1    Chu, C.2
  • 115
    • 33748605760 scopus 로고    scopus 로고
    • An efficient and effective detailed placement algorithm
    • M. Pan, N. Viswanathan, C. Chu, "An Efficient and Effective Detailed Placement Algorithm", ICCAD 2005, pp. 48-55.
    • (2005) ICCAD , pp. 48-55
    • Pan, M.1    Viswanathan, N.2    Chu, C.3
  • 116
    • 78650909876 scopus 로고    scopus 로고
    • SPIRE: A retiming-based physical-synthesis transformation system
    • D. A. Papa, S. Krishnaswamy, I. L. Markov, "SPIRE: A Retiming-based Physical-synthesis Transformation System", ICCAD 2010, pp. 373-380.
    • (2010) ICCAD , pp. 373-380
    • Papa, D.A.1    Krishnaswamy, S.2    Markov, I.L.3
  • 117
    • 78649262903 scopus 로고    scopus 로고
    • Speeding up physical synthesis with transactional timing analysis
    • D. A. Papa, M. D. Moffitt, C. J. Alpert, I. L. Markov, "Speeding Up Physical Synthesis with Transactional Timing Analysis", Design and Test 27(5) 2010, pp. 14-25.
    • (2010) Design and Test , vol.27 , Issue.5 , pp. 14-25
    • Papa, D.A.1    Moffitt, M.D.2    Alpert, C.J.3    Markov, I.L.4
  • 118
    • 56749100421 scopus 로고    scopus 로고
    • RUMBLE: An incremental, timing-driven, physical-synthesis optimization algorithm
    • D. A. Papa et al., "RUMBLE: An Incremental, Timing-driven, Physical-synthesis Optimization Algorithm", TCAD 27(12) 2008, pp. 2156-2168.
    • (2008) TCAD , vol.27 , Issue.12 , pp. 2156-2168
    • Papa, D.A.1
  • 119
    • 79961096575 scopus 로고    scopus 로고
    • Physical synthesis with clock-network optimization for large systems on chips
    • D. A. Papa, N. Viswanathan, C. N. Sze, Z. Li, G.-J. Nam, C. J. Alpert, I. L. Markov, "Physical Synthesis with Clock-Network Optimization for Large Systems on Chips", Micro 31(4) 2011, pp. 51-62.
    • (2011) Micro , vol.31 , Issue.4 , pp. 51-62
    • Papa, D.A.1    Viswanathan, N.2    Sze, C.N.3    Li, Z.4    Nam, G.-J.5    Alpert, C.J.6    Markov, I.L.7
  • 120
    • 0031635603 scopus 로고    scopus 로고
    • Congestion driven quadratic placement
    • P. N. Parakh, R. B. Brown, K. A. Sakallah, "Congestion Driven Quadratic Placement", DAC 1998, pp. 275-278.
    • (1998) DAC , pp. 275-278
    • Parakh, P.N.1    Brown, R.B.2    Sakallah, K.A.3
  • 121
    • 56749130513 scopus 로고    scopus 로고
    • Optimizing non-monotonic interconnect using functional simulation and logic restructuring
    • S. Plaza, I. L. Markov, V. Bertacco, "Optimizing Non-Monotonic Interconnect using Functional Simulation and Logic Restructuring", TCAD 27(12) 2008, pp. 2107-2119.
    • (2008) TCAD , vol.27 , Issue.12 , pp. 2107-2119
    • Plaza, S.1    Markov, I.L.2    Bertacco, V.3
  • 122
  • 123
    • 0042635592 scopus 로고    scopus 로고
    • Pushing ASIC performance in a power envelope
    • R. Puri et al., "Pushing ASIC Performance in a Power Envelope", DAC 2003, pp. 788-793.
    • (2003) DAC , pp. 788-793
    • Puri, R.1
  • 124
    • 0038379147 scopus 로고    scopus 로고
    • Timing driven force directed placement with physical net constraints
    • K. Rajagopal et al., "Timing Driven Force Directed Placement with Physical Net Constraints", ISPD 2003, pp. 60-66.
    • (2003) ISPD , pp. 60-66
    • Rajagopal, K.1
  • 125
    • 0029191105 scopus 로고
    • SPEED: Fast and efficient timing driven placement
    • B. M. Reiss, G. G. Ettelt, "SPEED: Fast and Efficient Timing Driven Placement", ISCAS 1995, pp. 377-380.
    • (1995) ISCAS , pp. 377-380
    • Reiss, B.M.1    Ettelt, G.G.2
  • 128
    • 18744384123 scopus 로고    scopus 로고
    • Sensitivity guided net weighting for placement driven synthesis
    • H. Ren, D. Z. Pan, D. S. Kung, "Sensitivity Guided Net Weighting for Placement Driven Synthesis", TCAD 24(5) 2005, pp. 711-721.
    • (2005) TCAD , vol.24 , Issue.5 , pp. 711-721
    • Ren, H.1    Pan, D.Z.2    Kung, D.S.3
  • 129
    • 33744778757 scopus 로고    scopus 로고
    • Min-cut floorplacement
    • J. A. Roy, S. N. Adya, D. A. Papa, I. L. Markov, "Min-cut Floorplacement", TCAD 25(7) 2006, pp.1313-1326.
    • (2006) TCAD , vol.25 , Issue.7 , pp. 1313-1326
    • Roy, J.A.1    Adya, S.N.2    Papa, D.A.3    Markov, I.L.4
  • 130
    • 33947609584 scopus 로고    scopus 로고
    • Seeing the forest and the trees: Steiner wirelength optimization in placement
    • J. A. Roy, I. L. Markov, "Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement", TCAD 23(4) 2007, pp. 632-644.
    • (2007) TCAD , vol.23 , Issue.4 , pp. 632-644
    • Roy, J.A.1    Markov, I.L.2
  • 131
    • 36348929500 scopus 로고    scopus 로고
    • ECO-system: Embracing the change in placement
    • J. A. Roy, I. L. Markov, "ECO-System: Embracing the Change in Placement", TCAD 26(12) 2007, pp. 2173-2185.
    • (2007) TCAD , vol.26 , Issue.12 , pp. 2173-2185
    • Roy, J.A.1    Markov, I.L.2
  • 133
    • 29144503209 scopus 로고    scopus 로고
    • Capo: Robust and scalable open-source min-cut floorplacer
    • vlsicad.eecs.umich.edu/BK/PDtools/
    • J. A. Roy et al., "Capo: Robust and Scalable Open-source Min-Cut Floorplacer", ISPD 2005, pp. 224-226, vlsicad.eecs.umich.edu/BK/PDtools/.
    • (2005) ISPD , pp. 224-226
    • Roy, J.A.1
  • 134
    • 76349116486 scopus 로고    scopus 로고
    • CRISP: Congestion reduction by iterated spreading during placement
    • J. A. Roy, N. Viswanathan, G.-J. Nam, C. J. Alpert, I. L. Markov, "CRISP: Congestion Reduction by Iterated Spreading during Placement", ICCAD 2009, pp. 357-362.
    • (2009) ICCAD , pp. 357-362
    • Roy, J.A.1    Viswanathan, N.2    Nam, G.-J.3    Alpert, C.J.4    Markov, I.L.5
  • 135
    • 0017430283 scopus 로고
    • Analytical power/timing optimization technique for digital systems
    • A. E. Ruehli, P. K. Wolff, G. Goertzel, "Analytical Power/Timing Optimization Technique for Digital Systems", DAC 1977, pp. 142-146.
    • (1977) DAC , pp. 142-146
    • Ruehli, A.E.1    Wolff, P.K.2    Goertzel, G.3
  • 136
    • 24944566140 scopus 로고    scopus 로고
    • Performance and low power driven vlsi standard cell placement using tabu search
    • S. M. Sait, M. R. Minhas, J. A. Khan, "Performance and Low Power Driven VLSI Standard Cell Placement using Tabu Search", Congress on Evolutionary Computation, 2002, pp. 372-377.
    • (2002) Congress on Evolutionary Computation , pp. 372-377
    • Sait, S.M.1    Minhas, M.R.2    Khan, J.A.3
  • 137
    • 0031378710 scopus 로고    scopus 로고
    • NRG: Global and detailed placement
    • M. Sarrafzadeh, M. Wang, "NRG: Global and Detailed Placement", ICCAD 1997, p. 532-537.
    • (1997) ICCAD , pp. 532-537
    • Sarrafzadeh, M.1    Wang, M.2
  • 138
    • 33748095768 scopus 로고    scopus 로고
    • On controlling perturbation due to repeaters during quadratic placement
    • P. Saxena, "On Controlling Perturbation Due to Repeaters during Quadratic Placement", TCAD 25(9) 2006, pp. 1733-1743.
    • (2006) TCAD , vol.25 , Issue.9 , pp. 1733-1743
    • Saxena, P.1
  • 139
    • 1442303508 scopus 로고    scopus 로고
    • Perimeter-degree: A priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement
    • N. Selvakkumaran, P. N. Parakh, G. Karypis, "Perimeter-degree: A Priori Metric for Directly Measuring and Homogenizing Interconnection Complexity in Multilevel Placement", SLIP 2003, pp. 53-59.
    • (2003) SLIP , pp. 53-59
    • Selvakkumaran, N.1    Parakh, P.N.2    Karypis, G.3
  • 140
    • 43349085862 scopus 로고    scopus 로고
    • Activity and register placement aware gated clock network design
    • W. Shen, Y. Cai, X. Hong, J. Hu, "Activity and Register Placement Aware Gated Clock Network Design", ISPD 2008, pp. 182-189.
    • (2008) ISPD , pp. 182-189
    • Shen, W.1    Cai, Y.2    Hong, X.3    Hu, J.4
  • 141
    • 0003291397 scopus 로고    scopus 로고
    • Monotone operators in banach space and nonlinear partial differential equations
    • Providence, RI: American Mathematical Society
    • R. E. Showalter, "Monotone Operators in Banach Space and Nonlinear Partial Differential Equations", Mathematical Surveys and Monographs 49. Providence, RI: American Mathematical Society, 1997, pp. 162-163.
    • (1997) Mathematical Surveys and Monographs 49 , pp. 162-163
    • Showalter, R.E.1
  • 142
    • 0026174925 scopus 로고
    • Analytical placement: A linear or a quadratic objective function?
    • G. Sigl, K. Doll, F. Johannes,"Analytical Placement: A Linear or a Quadratic Objective Function?" DAC 1991, pp. 427-432.
    • (1991) DAC , pp. 427-432
    • Sigl, G.1    Doll, K.2    Johannes, F.3
  • 143
    • 34548295220 scopus 로고    scopus 로고
    • Fast and accurate routing demand estimation for efficient routability-driven placement
    • P. Spindler, F. M. Johannes, "Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement",DATE 2007, pp. 1226-31.
    • (2007) DATE , pp. 1226-1231
    • Spindler, P.1    Johannes, F.M.2
  • 144
    • 43349095254 scopus 로고    scopus 로고
    • Abacus: Fast legalization of standard cell circuits with minimal movement
    • P. Spindler, U. Schlichtmann, F. M. Johannes, "Abacus: Fast Legalization of Standard Cell Circuits with Minimal Movement", ISPD 2008, pp. 47-53.
    • (2008) ISPD , pp. 47-53
    • Spindler, P.1    Schlichtmann, U.2    Johannes, F.M.3
  • 145
    • 47849103959 scopus 로고    scopus 로고
    • Kraftwerk2 - A fast force-directed quadratic placement approach using an accurate net model
    • P. Spindler, U. Schlichtmann, F.M. Johannes, "Kraftwerk2-A Fast Force-directed Quadratic Placement Approach using an Accurate Net Model", TCAD 27(8) 2008, pp. 1398-1411.
    • (2008) TCAD , vol.27 , Issue.8 , pp. 1398-1411
    • Spindler, P.1    Schlichtmann, U.2    Johannes, F.M.3
  • 146
    • 0027067732 scopus 로고
    • Ritual: A performance driven placement algorithm for small cell ICs
    • A. Srinivasan, K. Chaudhary, E. S. Kuh, "Ritual: A Performance Driven Placement Algorithm for Small Cell ICs", ICCAD 1991, pp. 48-51.
    • (1991) ICCAD , pp. 48-51
    • Srinivasan, A.1    Chaudhary, K.2    Kuh, E.S.3
  • 147
    • 0029226969 scopus 로고
    • Timing driven placement for large standard cell circuits
    • W. Swartz, C. Sechen, "Timing Driven Placement for Large Standard Cell Circuits", DAC 1995, pp. 211-215.
    • (1995) DAC , pp. 211-215
    • Swartz, W.1    Sechen, C.2
  • 148
    • 50549093705 scopus 로고    scopus 로고
    • Nonconvex gate delay modeling and delay optimization
    • H. Tennakoon, C. Sechen, "Nonconvex Gate Delay Modeling and Delay Optimization", TCAD 27(9) 2003, pp. 1583-1594.
    • (2003) TCAD , vol.27 , Issue.9 , pp. 1583-1594
    • Tennakoon, H.1    Sechen, C.2
  • 149
    • 0025568135 scopus 로고
    • A new min-cut placement algorithm for timing assurance layout design meeting net length constraint
    • M. Terai, K. Takahashi, K. Sato, "A New Min-cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint", DAC 1990, pp. 96-102.
    • (1990) DAC , pp. 96-102
    • Terai, M.1    Takahashi, K.2    Sato, K.3
  • 150
    • 1342323840 scopus 로고    scopus 로고
    • An integrated environment for technology closure of deep-submicron IC designs
    • L. Trevillyan, D. Kung, R. Puri, L. N. Reddy, M. A. Kazda, "An Integrated Environment for Technology Closure of Deep-Submicron IC Designs", Design and Test 21(1) 2004, pp. 14-22.
    • (2004) Design and Test , vol.21 , Issue.1 , pp. 14-22
    • Trevillyan, L.1    Kung, D.2    Puri, R.3    Reddy, L.N.4    Kazda, M.A.5
  • 151
    • 84872295234 scopus 로고
    • An analytic net weighting approach for performance optimization in circuit placement
    • R. S. Tsay, J. Koehl, "An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement", DAC 1991, pp. 636-639.
    • (1991) DAC , pp. 636-639
    • Tsay, R.S.1    Koehl, J.2
  • 152
    • 57849159088 scopus 로고    scopus 로고
    • Guiding global placement with wire density
    • K. Tsota, C. Koh, V. Balakrishnan, "Guiding Global Placement with Wire Density", ICCAD 2008, pp. 212-217.
    • (2008) ICCAD , pp. 212-217
    • Tsota, K.1    Koh, C.2    Balakrishnan, V.3
  • 153
    • 0027808919 scopus 로고
    • PCUBE: A performance driven placement algorithm for low power designs
    • H. Vaishnav, M. Pedram, "PCUBE: A Performance Driven Placement Algorithm for Low Power Designs", DAC with EURO-VHDL, 1993, pp.72-77.
    • (1993) DAC with EURO-VHDL , pp. 72-77
    • Vaishnav, H.1    Pedram, M.2
  • 154
    • 0025594311 scopus 로고
    • Buffer placement in distributed rc-tree network for minimal elmore delay
    • L. P. P. P. van Ginneken, "Buffer Placement in Distributed RC-tree Network for Minimal Elmore Delay", ISCAS 1990, pp. 865-868.
    • (1990) ISCAS , pp. 865-868
    • Van Ginneken, L.P.P.P.1
  • 155
    • 79955066226 scopus 로고    scopus 로고
    • The ISPD-2011 routability-driven placement contest and benchmark suite
    • N. Viswanathan, C. J. Alpert, Z. Li, G.-J. Nam, J. A. Roy, "The ISPD-2011 Routability-driven Placement Contest and Benchmark Suite", ISPD 2011, pp. 141-146.
    • (2011) ISPD , pp. 141-146
    • Viswanathan, N.1    Alpert, C.J.2    Li, Z.3    Nam, G.-J.4    Roy, J.A.5
  • 156
    • 84863558267 scopus 로고    scopus 로고
    • The DAC 2012 routability-driven placement contest and benchmark suite
    • N. Viswanathan, C. J. Alpert, C. N. Sze, Z. Li, Y. Wei, "The DAC 2012 Routability-driven Placement Contest and Benchmark Suite", DAC 2012, pp. 774-782.
    • (2012) DAC , pp. 774-782
    • Viswanathan, N.1    Alpert, C.J.2    Sze, C.N.3    Li, Z.4    Wei, Y.5
  • 157
    • 34547326796 scopus 로고    scopus 로고
    • FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control
    • N. Viswanathan, M. Pan, C. Chu, "FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control", ASPDAC 2007, pp. 135-140.
    • (2007) ASPDAC , pp. 135-140
    • Viswanathan, N.1    Pan, M.2    Chu, C.3
  • 158
    • 34547345140 scopus 로고    scopus 로고
    • RQL: Global placement via relaxed quadratic spreading and linearization
    • N. Viswanathan, G.-J. Nam, C. J. Alpert, P. G. Villarrubia, H. Ren, "RQL: Global Placement via Relaxed Quadratic Spreading and Linearization", DAC 2007, pp. 453-458.
    • (2007) DAC , pp. 453-458
    • Viswanathan, N.1    Nam, G.-J.2    Alpert, C.J.3    Villarrubia, P.G.4    Ren, H.5
  • 159
    • 4444239809 scopus 로고    scopus 로고
    • Efficient timing closure without timing driven placement and routing
    • M. Vujkovic, D. Wadkins, B. Swartz, C. Sechen, "Efficient Timing Closure without Timing Driven Placement and Routing",DAC 2004, pp. 268-73.
    • (2004) DAC , pp. 268-273
    • Vujkovic, M.1    Wadkins, D.2    Swartz, B.3    Sechen, C.4
  • 160
    • 84863543772 scopus 로고    scopus 로고
    • PADE: A high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning
    • S. Ward, D. Ding, D. Z. Pan, "PADE: A High-performance Placer with Automatic Datapath Extraction and Evaluation Through High Dimensional Data Learning", DAC 2012, pp. 756-761.
    • (2012) DAC , pp. 756-761
    • Ward, S.1    Ding, D.2    Pan, D.Z.3
  • 161
    • 0032689921 scopus 로고    scopus 로고
    • On the behaviour of congestion minimization during placement
    • M. Wang, M. Sarrafzadeh, "On the Behaviour of Congestion Minimization during Placement", ISPD 1999, pp. 145-150.
    • (1999) ISPD , pp. 145-150
    • Wang, M.1    Sarrafzadeh, M.2
  • 162
    • 84884678446 scopus 로고    scopus 로고
    • Model and minimization of routing congestion
    • M. Wang, M. Sarrafzadeh, "Model and Minimization of Routing Congestion", ASPDAC 2000, pp. 185-190.
    • (2000) ASPDAC , pp. 185-190
    • Wang, M.1    Sarrafzadeh, M.2
  • 163
    • 0034296451 scopus 로고    scopus 로고
    • Congestion minimization during placement
    • M. Wang X. Yang, M. Sarrafzadeh, "Congestion Minimization during Placement", in TCAD 19(10) 2000, pp. 1140-1148.
    • (2000) TCAD , vol.19 , Issue.10 , pp. 1140-1148
    • Wang X Yang, M.1    Sarrafzadeh, M.2
  • 164
    • 0033718021 scopus 로고    scopus 로고
    • Multicenter congestion estimation and minimization during placement
    • M. Wang, X. Yang, K. Eguro, M. Sarrafzadeh, "Multicenter Congestion Estimation and Minimization during Placement",ISPD 2000, pp. 147-152.
    • (2000) ISPD , pp. 147-152
    • Wang, M.1    Yang, X.2    Eguro, K.3    Sarrafzadeh, M.4
  • 165
    • 34548845359 scopus 로고    scopus 로고
    • Clock-tree aware placement based on dynamic clock-tree building
    • Y. Wang, Q. Zhou, X. Hong, Y. Cai, "Clock-tree Aware Placement Based on Dynamic Clock-tree Building", ISCAS 2007, pp. 2040-2043.
    • (2007) ISCAS , pp. 2040-2043
    • Wang, Y.1    Zhou, Q.2    Hong, X.3    Cai, Y.4
  • 166
    • 34547346784 scopus 로고    scopus 로고
    • Hard macros will revolutionize soc design
    • August 20
    • E. Wein, J. Benkoski, "Hard Macros Will Revolutionize SoC Design", EE Times Online, August 20, 2004. http://www.eetimes.com/news/ design/showArtical.jhtml?articalID=26807055
    • (2004) EE Times Online
    • Wein, E.1    Benkoski, J.2
  • 167
    • 50249173469 scopus 로고    scopus 로고
    • Timing optimization by restructuring long combinatorial paths
    • J. Werber, D. Rautenbach, C. Szegedy, "Timing Optimization by Restructuring Long Combinatorial Paths", ICCAD 2007, pp. 536-543.
    • (2007) ICCAD , pp. 536-543
    • Werber, J.1    Rautenbach, D.2    Szegedy, C.3
  • 168
    • 2942632936 scopus 로고    scopus 로고
    • Probabilistic congestion prediction
    • J. Westra, C. Bartels, P. Groeneveld, "Probabilistic Congestion Prediction", ISPD 2004, pp. 204-209.
    • (2004) ISPD , pp. 204-209
    • Westra, J.1    Bartels, C.2    Groeneveld, P.3
  • 169
    • 30944433213 scopus 로고    scopus 로고
    • Is probabilistic congestion estimation worthwhile?
    • J. Westra, P. Groeneveld, "Is Probabilistic Congestion Estimation Worthwhile?" SLIP 2005, pp. 99-106.
    • (2005) SLIP , pp. 99-106
    • Westra, J.1    Groeneveld, P.2
  • 172
    • 27944435301 scopus 로고    scopus 로고
    • Timing-driven placement by grid-warping
    • Zhong Xiu, R. Rutenbar, "Timing-driven Placement by Grid-warping", DAC 2005, pp. 585-590.
    • (2005) DAC , pp. 585-590
    • Xiu, Z.1    Rutenbar, R.2
  • 173
    • 64549091868 scopus 로고    scopus 로고
    • FastRoute 4.0: Global router with efficient via minimization
    • Y. Xu, Y. Zhang, C. Chu, "FastRoute 4.0: Global Router with Efficient Via Minimization", ASPDAC 2009, pp. 576-581.
    • (2009) ASPDAC , pp. 576-581
    • Xu, Y.1    Zhang, Y.2    Chu, C.3
  • 174
    • 70350714592 scopus 로고    scopus 로고
    • Handling complexities in modern large-scale mixed-size placement
    • J. Z. Yan, N. Viswanathan, C. Chu, "Handling Complexities in Modern Large-scale Mixed-size Placement", DAC 2009, pp. 436-441.
    • (2009) DAC , pp. 436-441
    • Yan, J.Z.1    Viswanathan, N.2    Chu, C.3
  • 175
    • 0037387687 scopus 로고    scopus 로고
    • Routability-driven white space allocation for fixed-die standard-cell placement
    • X. Yang, B.-K. Choi, M. Sarrafzadeh, "Routability-driven White Space Allocation for Fixed-die Standard-cell Placement", TCAD 22(4) 2003, pp. 410-419.
    • (2003) TCAD , vol.22 , Issue.4 , pp. 410-419
    • Yang, X.1    Choi, B.-K.2    Sarrafzadeh, M.3
  • 176
    • 0032690059 scopus 로고    scopus 로고
    • Layout techniques supporting the use of dual supply voltages for cell-based designs
    • C. Yeh, Y. Kang, S. Shieh, J. Wang, "Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs",DAC 1999, pp. 62-67.
    • (1999) DAC , pp. 62-67
    • Yeh, C.1    Kang, Y.2    Shieh, S.3    Wang, J.4
  • 177
    • 0025556064 scopus 로고
    • Timing constraints for correct peformance
    • H. Youssef, E. Shragowitz, "Timing Constraints for Correct Peformance", ICCAD 1990, pp. 24-27.
    • (1990) ICCAD , pp. 24-27
    • Youssef, H.1    Shragowitz, E.2
  • 178
    • 76349107355 scopus 로고    scopus 로고
    • CROP: Fast and effective congestion refinement of placement
    • Y. Zhang, C. Chu, "CROP: Fast and Effective Congestion Refinement of Placement", ICCAD 2009, pp. 344-350.
    • (2009) ICCAD , pp. 344-350
    • Zhang, Y.1    Chu, C.2
  • 179
    • 0036044627 scopus 로고    scopus 로고
    • Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control
    • K. Zhong, S. Dutt, "Algorithms for Simultaneous Satisfaction of Multiple Constraints and Objective Optimization in a Placement Flow with Application to Congestion Control", DAC 2002, pp. 854-859.
    • (2002) DAC , pp. 854-859
    • Zhong, K.1    Dutt, S.2


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