Guiding global placement with wire density

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 212-217

  Tsota, Kalliopi ^a   Koh, Cheng Kok ^a   Balakrishnan, Venkataramanan ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL PLACEMENTS; BENCHMARK SUITES; LEVEL STRUCTURES; OBJECTIVE FUNCTIONS; WIRE LENGTHS;

COMPUTER AIDED DESIGN;

WIRE;

EID: 57849159088     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681576     Document Type: Conference Paper

References (22)

1. C.-L. E. Cheng, "RISA: Accurate and efficient placement routability modeling," in Proc. IEEE/ACM International Conference on ComputerAided Design, San Jose, California, Nov. 1994, pp. 690-695.
2. M. Wang, X. Yang, and M. Sarrafzadeh, "Congestion minimization during placement," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1140-1148, Oct. 2000.
3. J. Lou, T. S. Krishnamoorthy, and H. S. Sheng, "Estimating routing congestion using probabilistic analysis," in Proc. ACM/S1GDA International Symposium on Physical Design, Sonoma, California, Jan. 2001, pp. 112-117.
4. W. Hou, H. Yu, X. Hong, Y. Cai, W. Wu, J. Gu, and W. Kao, "A new congestion-driven placement algorithm based on cell inflation," in Proc. Asia and South Pacific Design Automation Conference, Yokohama, Japan, Jan. 2001, pp. 605-608.
5. U. Brenner and A. Rohe, "An effective congestion-driven placement framework," in Proc. ACM/SIGDA International Symposium on Physical Design, San Diego, California, Jan. 2002, pp. 6-11.
6. Z. Li, W. Wu, and X. Hong, "Congestion-driven incremental placement algorithm for standard cell layout," in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, Kitakyushu, Japan, Jan. 2003, pp. 723-728.
7. X. Yang, R. Kashner, and M. Sarrafzadeh, "Congestion estimation during top-down placement," IEEE Trans. Computer-Aided Design, vol. 21, pp. 72-80, Jan. 2002.
8. B. Hu and M. Marek-Sadowska, "Congestion minimization during placement without estimation," in Proc. IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, Nov. 2002, pp. 739-745.
9. M. Wang and M. Sarrafzadeh, "Modeling and minimization of routing congestion," in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, Yokohama, Japan, Jan. 2000, pp. 185-290.
10. P. Spindler and F. Johannes, "Fast and accurate routing demand estimation for efficient routability-driven placement," in Proc. Design Automation and Test in Europe Conference, Nice, France, Apr. 2007, pp. 1-6.
11. A. B. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer," IEEE Trans. Computer-Aided Design, vol. 24, pp. 734-747, May 2005.
12. C. Li and C.-K. Koh, "Recursive function smoothing of half-perimeter wirelength for analytical placement," in Proc. International Symposium on Quality Electronic Design, San Jose, California, Mar. 2007, pp. 829834.
13. C. Li, M. Xie, C.-K. Koh, J. Cong, and P. H. Madden, " Routahilitydriven placement and white space allocation," in Proc. International Conference on Computer-Aided Design, San Jose, California, Nov. 2004, pp. 394-401.
14. T. Chan, J. Cong, M. Romesis, J. R. Shinnerl, K. Sze, and M. Xie, "mPL6: A robust multilevel mixed-size placement engine," in Proc. ACM/SIGDA International Symposium on Physical Design, San Fransisco, California, Apr. 2005, pp. 227-229.
15. J. A. Roy and I. L. Markov, "Seeing the forest and the trees: Steiner wirelength optimization in placement," IEEE Trans. Computer-Aided Design, vol. 26, pp. 632-644, Apr. 2007.
16. A. B. Kahng, S. Reda, and Q. Wang, "Architecture and details of a highquality, large-scale analytical placer," in Proc. IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, Nov. 2005, pp. 891-898.
17. W. Naylor, R. Donelly, and L. Sha, "Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer," U.S. Patent 6301 693, Oct. 09, 2001.
18. S. Birbil, S. Fang, H. Frenk, and S. Zhang, "Recursive approximation of the high-dimensional max function," Department of Systems Engineering and Engineering Management SEEM, The Chinese University of Hong Kong, HK, Tech. Rep. SEEM 2002-12, Dec. 2002.
19. G. Karypis and V. Kumar, "Multilevel K-way hypergraph partitioning," IEEE Trans. VLSI Syst., vol. 11, pp. 285-300, Jan. 2000.
20. G. Karypis, R. Aggarwal, V. Kumar, and S.Shekhar, "Multilevel K-way hypergraph partitioning: Applications in VLSI domain," IEEE Trans. VLSI Syst., vol. 7, pp. 69-79, Mar. 1.999.
21. N. Selvakkumaran and G. Karypis, "Multi-objective hypergraph partitioning algorithms for cut and maximum subdomain degree minimization," IEEE Trans. Computer-Aided Design, vol. 25, pp. 504-517, Mar. 2006.
22. C. Zhu, R. Byrd, and J. Nocedal, "L-BFGS-B, FORTRAN routines for large-scale bound constrained optimization," ACM Transactions on Mathematical Software, vol. 23, pp. 550-560, Dec. 1997.