RBI: Simultaneous placement and routing optimization technique

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 1, 2007, Pages 127-141

  Jariwala, Devang ^a,b   Lillis, John ^a,b  

^a IEEE   (United States)

^b University of Illinois at Chicago   (United States)

Author keywords

Design automation; Integrated circuit layout; Placement; Routing; Simultaneous placement and routing optimization

Indexed keywords

DESIGN AUTOMATION; ROUTING OPTIMIZATION; SIMULTANEOUS PLACEMENT; VERSATILE PLACE AND ROUTE (VPR);

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION; PROBABILISTIC LOGICS;

INTEGRATED CIRCUIT LAYOUT;

EID: 33846239297     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.883918     Document Type: Article

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