-
1
-
-
0036375925
-
Min-Max placement for large-scale timing optimization
-
A. Kahng, S. Mantik, and I. L. Markov, "Min-Max placement for large-scale timing optimization," in Proc. ACM Int. Symp. Phys. Design, 2002, pp. 143-148.
-
(2002)
Proc. ACM Int. Symp. Phys. Design
, pp. 143-148
-
-
Kahng, A.1
Mantik, S.2
Markov, I.L.3
-
2
-
-
1542269353
-
Simultaneous Vt selection and assignment for leakage optimization
-
A. Srivastava, "Simultaneous Vt selection and assignment for leakage optimization," in Proc. Int. Symp. Low Power Electron. Design, 2003, pp. 146-151.
-
(2003)
Proc. Int. Symp. Low Power Electron. Design
, pp. 146-151
-
-
Srivastava, A.1
-
3
-
-
0043151300
-
Budget management with applications
-
Jul.
-
C. Chen, E. Bozorgzadeh, A. Srivastava, and M. Sarrafzadeh, "Budget management with applications," Algorithmic, vol. 34, no. 3, pp. 261-275, Jul. 2002.
-
(2002)
Algorithmic
, vol.34
, Issue.3
, pp. 261-275
-
-
Chen, C.1
Bozorgzadeh, E.2
Srivastava, A.3
Sarrafzadeh, M.4
-
4
-
-
0034481127
-
Potential slack: An effective metric of combinational circuit performance
-
C. Chen, X. Yang, and M. Sarrafzadeh, "Potential slack: An effective metric of combinational circuit performance," in Proc. ACM/IEEE Int. Conf. Computer-Aided Design, 2000, pp. 198-201.
-
(2000)
Proc. ACM/IEEE Int. Conf. Computer-Aided Design
, pp. 198-201
-
-
Chen, C.1
Yang, X.2
Sarrafzadeh, M.3
-
6
-
-
0031339427
-
MediaBench: A tool for evaluating and synthesizing multimedia and communications systems
-
C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "MediaBench: A tool for evaluating and synthesizing multimedia and communications systems," in Proc. Int. Symp. Microarchitecture, 1997, pp. 330-335.
-
(1997)
Proc. Int. Symp. Microarchitecture
, pp. 330-335
-
-
Lee, C.1
Potkonjak, M.2
Mangione-Smith, W.H.3
-
7
-
-
0043136763
-
Delay budgeting in sequential circuit with application on FPGA placement
-
C. Yeh and M. Marek-Sadowska, "Delay budgeting in sequential circuit with application on FPGA placement," in Proc. ACM/IEEE Design Automation Conf., 2003, pp. 202-207.
-
(2003)
Proc. ACM/IEEE Design Automation Conf.
, pp. 202-207
-
-
Yeh, C.1
Marek-Sadowska, M.2
-
8
-
-
0031364697
-
Maximum independent sets on transitive graphs and their applications in testing and CAD
-
D. Kagaris and S. Tragoudas, "Maximum independent sets on transitive graphs and their applications in testing and CAD," in Proc. Int. Conf. Computer-Aided Design, 1997, pp. 736-740.
-
(1997)
Proc. Int. Conf. Computer-Aided Design
, pp. 736-740
-
-
Kagaris, D.1
Tragoudas, S.2
-
10
-
-
0042883398
-
A polynomial algorithm for balancing acyclic data flow graphs
-
Nov.
-
E. Boros, P. Hammer, and R. Shamir, "A polynomial algorithm for balancing acyclic data flow graphs," IEEE Trans. Comput., vol. 41, no. 11, pp. 1380-1385, Nov. 1992.
-
(1992)
IEEE Trans. Comput.
, vol.41
, Issue.11
, pp. 1380-1385
-
-
Boros, E.1
Hammer, P.2
Shamir, R.3
-
11
-
-
38149147744
-
Balancing problems in acyclic networks
-
Mar.
-
E. Boros, P. Hammer, M. Hartmann, and R. Shamir, "Balancing problems in acyclic networks," Discr. Appl. Math., vol. 49, no. 1-3, pp. 77-93, Mar. 1994.
-
(1994)
Discr. Appl. Math
, vol.49
, Issue.1-3
, pp. 77-93
-
-
Boros, E.1
Hammer, P.2
Hartmann, M.3
Shamir, R.4
-
12
-
-
0041633577
-
Optimal integer delay budgeting on directed acyclic graphs
-
Jun.
-
E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, "Optimal integer delay budgeting on directed acyclic graphs," in Proc. Design Automation Conf., Jun. 2003, pp. 920-925.
-
(2003)
Proc. Design Automation Conf.
, pp. 920-925
-
-
Bozorgzadeh, E.1
Ghiasi, S.2
Takahashi, A.3
Sarrafzadeh, M.4
-
13
-
-
3843057942
-
Optimal integer delay budget assignment on directed acyclic graphs
-
Aug.
-
_, "Optimal integer delay budget assignment on directed acyclic graphs," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 8, pp. 1184-1199, Aug. 2004.
-
(2004)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.23
, Issue.8
, pp. 1184-1199
-
-
-
14
-
-
0026995131
-
An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints
-
Nov.
-
E. Felt, E. Charbon, E. Malavasi, and A. Sangiovanni-Vincentelli, "An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints," in Proc. Conf. Eur. Design Automation, Nov. 1992, pp. 148-153.
-
(1992)
Proc. Conf. Eur. Design Automation
, pp. 148-153
-
-
Felt, E.1
Charbon, E.2
Malavasi, E.3
Sangiovanni-Vincentelli, A.4
-
15
-
-
84982859985
-
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling
-
Sep.
-
F. Xie, M. Martonosi, and S. Malik, "Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling," ACM Trans. Archit. Code Optimization, vol. 1, no. 3, pp. 323-367, Sep. 2004.
-
(2004)
ACM Trans. Archit. Code Optimization
, vol.1
, Issue.3
, pp. 323-367
-
-
Xie, F.1
Martonosi, M.2
Malik, S.3
-
16
-
-
0029539754
-
Power reduction by gate sizing with path-oriented slack calculation
-
H. R. Lin and T. Hwang, "Power reduction by gate sizing with path-oriented slack calculation," in Proc. IEEE ASPDAC, 1995, pp. 7-12.
-
(1995)
Proc. IEEE ASPDAC
, pp. 7-12
-
-
Lin, H.R.1
Hwang, T.2
-
18
-
-
0034842269
-
Battery-aware static scheduling for distributed real-time embedded systems
-
J. Luo and N. Jha, "Battery-aware static scheduling for distributed real-time embedded systems," in Proc. IEEE/ACM Design Automation Conf., 2001, pp. 444-449.
-
(2001)
Proc. IEEE/ACM Design Automation Conf.
, pp. 444-449
-
-
Luo, J.1
Jha, N.2
-
19
-
-
0041648453
-
VLSI layout compaction with grid and mixed constraints
-
Sep.
-
J. F. Lee and D. T. Tang, "VLSI layout compaction with grid and mixed constraints," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. CAD-6, no. 5, pp. 903-910, Sep. 1987.
-
(1987)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.CAD-6
, Issue.5
, pp. 903-910
-
-
Lee, J.F.1
Tang, D.T.2
-
20
-
-
0030651855
-
Unification of budgeting and placement
-
Jun.
-
M. Sarrafzadeh, D. Knol, and G. E. Tellez, "Unification of budgeting and placement," in Proc. ACM/IEEE Design Automation Conf., Jun. 1997, pp. 758-761.
-
(1997)
Proc. ACM/IEEE Design Automation Conf.
, pp. 758-761
-
-
Sarrafzadeh, M.1
Knol, D.2
Tellez, G.E.3
-
21
-
-
0346868278
-
An introduction to machine SUIF and its portable libraries for analysis and optimization
-
Cambridge, MA. [Online]. Available
-
M. D. Smith and G. Holloway. (2005). "An introduction to machine SUIF and its portable libraries for analysis and optimization," Division Eng. Appl. Sci., Harvard Univ. Cambridge, MA. [Online]. Available: http://www.eecs.harvard.edu/hube/software/nci/overview.html
-
(2005)
Division Eng. Appl. Sci., Harvard Univ.
-
-
Smith, M.D.1
Holloway, G.2
-
22
-
-
0031273491
-
A delay budgeting algorithm ensuring maximum flexibility in placement
-
Nov.
-
M. Sarrafzadeh, D. A. Knol, and G. E. Tellez, "A delay budgeting algorithm ensuring maximum flexibility in placement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 16, no. 11, pp. 1332-1341, Nov. 1997.
-
(1997)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.16
, Issue.11
, pp. 1332-1341
-
-
Sarrafzadeh, M.1
Knol, D.A.2
Tellez, G.E.3
-
23
-
-
0030380793
-
Maximizing multiprocessor performance with the SUIF compiler
-
Dec.
-
M. W. Hall, J. M. Anderson, S. P. Amarasinghe, B. R. Murphy, L. Shih-Wei, E. Bugnion, and M. S. Lam, "Maximizing multiprocessor performance with the SUIF compiler," Computer, vol. 29, no. 12, pp. 84-89, Dec. 1996.
-
(1996)
Computer
, vol.29
, Issue.12
, pp. 84-89
-
-
Hall, M.W.1
Anderson, J.M.2
Amarasinghe, S.P.3
Murphy, B.R.4
Shih-Wei, L.5
Bugnion, E.6
Lam, M.S.7
-
25
-
-
0030689996
-
A gate resizing technique for high reduction in power consumption
-
P. Girard, C. Landrault, S. Pravossoudovitch, and D. Severac, "A gate resizing technique for high reduction in power consumption," in Proc. Int. Symp. Low Power Electron. Design, 1997, pp. 281-286.
-
(1997)
Proc. Int. Symp. Low Power Electron. Design
, pp. 281-286
-
-
Girard, P.1
Landrault, C.2
Pravossoudovitch, S.3
Severac, D.4
-
26
-
-
0003515463
-
-
Englewood Cliffs, NJ: Prentice-Hall
-
T. Magnanti, R. Ahuja, and J. Orlin, Network Flows: Theory, Algorithms, and Applications. Englewood Cliffs, NJ: Prentice-Hall, 1993.
-
(1993)
Network Flows: Theory, Algorithms, and Applications
-
-
Magnanti, T.1
Ahuja, R.2
Orlin, J.3
-
27
-
-
0024716080
-
Generation of performance constraints for layout
-
Aug.
-
R. Nair, C. Berman, P. Hauge, and E. Yoffa, "Generation of performance constraints for layout," IEEE Trans, Comput.-Aided Design Integr. Circuits Syst., vol. 8, no. 8, pp. 860-874, Aug. 1989.
-
(1989)
IEEE Trans, Comput.-Aided Design Integr. Circuits Syst.
, vol.8
, Issue.8
, pp. 860-874
-
-
Nair, R.1
Berman, C.2
Hauge, P.3
Yoffa, E.4
-
28
-
-
0030166226
-
Component selection for high-performance pipelines
-
Jun.
-
S. Bakshi and D. Gajski, "Component selection for high-performance pipelines," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 4, no. 2, pp. 181-194, Jun. 1996.
-
(1996)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.4
, Issue.2
, pp. 181-194
-
-
Bakshi, S.1
Gajski, D.2
-
29
-
-
33747386295
-
Efficient implementation selection via time budgeting: Complexity analysis and leakage optimization case study
-
S. Ghiasi, "Efficient implementation selection via time budgeting: Complexity analysis and leakage optimization case study," in Proc. Int. Conf. Computer Design, 2005, pp. 127-129.
-
(2005)
Proc. Int. Conf. Computer Design
, pp. 127-129
-
-
Ghiasi, S.1
-
30
-
-
16244366792
-
A unified theory of timing budget management
-
S. Ghiasi, E. Bozorgzadeh, S. Choudhury, and M. Sarrafzadeh, "A unified theory of timing budget management," in Proc, IEEE/ACM Int. Conf. Computer-Aided Design, 2004, pp. 653-659.
-
(2004)
Proc, IEEE/ACM Int. Conf. Computer-Aided Design
, pp. 653-659
-
-
Ghiasi, S.1
Bozorgzadeh, E.2
Choudhury, S.3
Sarrafzadeh, M.4
-
31
-
-
1542537818
-
On computation and resource management in networked embedded systems
-
S. Ghiasi, K. Nguyen, E. Bozorgzadeh, and M. Sarrafzadeh, "On computation and resource management in networked embedded systems," in Proc. Int. Conf. Parallel Distrib. Computer Syst., 2003, pp. 445-451.
-
(2003)
Proc. Int. Conf. Parallel Distrib. Computer Syst.
, pp. 445-451
-
-
Ghiasi, S.1
Nguyen, K.2
Bozorgzadeh, E.3
Sarrafzadeh, M.4
-
32
-
-
0031247931
-
Scheduling with multiple voltages
-
Oct.
-
S. Raje and M. Sarrafzadeh, "Scheduling with multiple voltages," Integration, vol. 23, no. 1, pp. 37-59, Oct. 1997.
-
(1997)
Integration
, vol.23
, Issue.1
, pp. 37-59
-
-
Raje, S.1
Sarrafzadeh, M.2
-
34
-
-
0036907067
-
A novel net weighting algorithm for timing-driven placement
-
T. Kong, "A novel net weighting algorithm for timing-driven placement," in Proc. ACM/IEEE Int. Conf. Computer-Aided Design, 2002, pp. 172-176.
-
(2002)
Proc. ACM/IEEE Int. Conf. Computer-Aided Design
, pp. 172-176
-
-
Kong, T.1
-
35
-
-
0035694661
-
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction
-
W. Zhang, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D. Duarte, and Y. Tsai, "Exploiting VLIW schedule slacks for dynamic and leakage energy reduction," in Proc. ACM/IEEE Int. Symp. Microarchitecture, 2001, pp. 102-113.
-
(2001)
Proc. ACM/IEEE Int. Symp. Microarchitecture
, pp. 102-113
-
-
Zhang, W.1
Vijaykrishnan, N.2
Kandemir, M.3
Irwin, M.J.4
Duarte, D.5
Tsai, Y.6
-
36
-
-
0020734713
-
An algorithm to compact a VLSI symbolic layout with mixed constraints
-
Apr.
-
Y. Liao and C. K. Wong, "An algorithm to compact a VLSI symbolic layout with mixed constraints," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. CAD-2, no. 2, pp. 62-69, Apr. 1983.
-
(1983)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.CAD-2
, Issue.2
, pp. 62-69
-
-
Liao, Y.1
Wong, C.K.2
|