PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2011, Pages 85-90

  Chuang, Yi Lin ^a   Lin, Hong Ting ^b   Ho, Tsung Yi ^b   Chang, Yao Wen ^a   Marculescu, Diana ^c  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PLACEMENT; CLOCK NETWORK; ITERATIVE IMPROVEMENTS; PHYSICAL SYNTHESIS; POWER REDUCTIONS; TIMING SLACK;

COMPUTER AIDED DESIGN; OPTIMIZATION;

CLOCKS;

EID: 84862908140     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105310     Document Type: Conference Paper

References (15)

1. T. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie. mPL6: Enhanced multilevel mixed-size placement. In Proc. of ISPD, 2006.
2. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. In IEEE TCAD, 2008.
3. Y. Cheon, P.-H. Ho, A. B. Kahng, S. Reda, and Q. Wang. Power-aware placement. In Proc. of DAC, 2005.
4. Y.-L. Chuang, S. Kim, Y. Shin, and Y.-W. Chang. Pulsed-latch-aware placement for timing-integrity optimization. In Proc. of DAC, 2010.
5. M. Edahiro. A clustering-based optimization algorithm in zero-skew routings. In Proc. of DAC, 1993.
6. IWLS 2005 Benchmarks. http://iwls.org/iwls2005/benchmarks.html.
7. A. B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. In IEEE TCAD, 2005.
8. H. Lee, S. Paik, and Y. Shin. Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. In Proc. of ICCAD, 2008.
9. H.-C. Li, M.-C. Chen, and K. Ho. System and method of replacing flip-flops with pulsed latches in circuit designs. U.S. Patent 7 694 242, 2010.
10. H.-T. Lin, Y.-L. Chuang, and T.-Y. Ho. Pulsed-Latch-Based Clock Tree Migration for Dynamic Power Reduction. In Proc. of ISLPED, 2011.
11. W. C. Naylor, R. Donelly, and L. Sha. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. U.S. Patent 6 301 693, 2001.
12. OpenCores. http://www.opencores.org.
13. W. Shen, Y. Cai, X. Hong, and J. Hu. Activity and register placement placement aware gated clock network design. In Proc. of ISPD, 2008.
14. S. Shibatani and A. H.C. Li. Pulse-latch approach reduces dynamic power. EETimes Online, 2006.
15. V. Shukla. Low power ICD talks. Cadence, 2007.