Porosity aware buffered steiner tree construction

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2003, Pages 158-165

  Alpert, Charles J ^a   Gandham, Gopal ^a   Hrkic, Milos ^b   Hu, Jiang ^c   Quay, Stephen T ^a  

^a IBM   (United States)

^b UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

^c TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Buffer insertion; Interconnect; Physical design; VLSI

Indexed keywords

ALGORITHMS; PROBLEM SOLVING; TREES (MATHEMATICS); VLSI CIRCUITS;

BUFFER INSERTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0038040192     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/640000.640035     Document Type: Conference Paper

References (17)

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