Navigating registers in placement for clock network minimization

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 176-181

  Lu, Yongqiang ^a   Sze, C N ^b   Hong, Xianlong ^a   Zhou, Qiang ^a   Cai, Yici ^a   Huang, Liang ^a   Hu, Jiang ^b  

^a TSINGHUA UNIVERSITY   (China)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Clock network; Low power; Placement; Variation tolerance

Indexed keywords

CONSTRAINT THEORY; ENERGY UTILIZATION; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

CLOCK NETWORKS; LOW POWER; PLACEMENT; VARIATION TOLERANCE;

ELECTRIC CLOCKS;

EID: 27944447299     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065579.1065628     Document Type: Conference Paper

References (16)

1. D. E. Duate, N. Vijaykrishnan and M. J. Irwin, "A clock power model to evaluate impact of architectural and technology optimization," in IEEE TVLSI, 10(6): 844-855, Dec. 2002.
2. S. Zhao, K. Roy and C.-K. Koh, "Estimation of inductive and resistive switching noise on power supply network in deep sub-micron CMOS circuits," in Proc. IEEE ICCD, pp. 65-72, 2000.
3. S. Zanella, A. Nardi, A. Neviani, M. Quarantelli, S. Saxena and C. Guardiani, "Analysis of the impact of process variations on clock skew," in IEEE Transactions on Semiconductor Manufacturing, 13(4): 401-407, Nov. 2000.
4. T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese and A. B. Kahng, "Zero skew clock routing with minimum wirelength," in IEEE Transactions on Circuits & Systems II: Analog & Digital Signal Processing, 39 (11): 799-814, Nov. 1992.
5. J. Cong, A. B. Kahng, C.-K. Koh and C.-W. A. Tsao, "Bounded-skew clock and Steiner routing," in ACM TODAES, 3(3): 341-388, Jul. 1998.
6. R. Chaturvedi and J. Hu, "A simple yet effective merging scheme for prescribed-skew clock routing," in Proc. IEEE ICCD, pp. 282-287, 2003.
7. C.-W. A. Tsao and C.-K. Koh, "UST/DME: a clock tree router for general skew constraints," in Proc. IEEE/ACM ICCAD, pp. 400-405, 2000.
8. R. B. Deokar and S. S. Sapatnekar, "A graph-theoretic approach to clock skew optimization", in Proc. IEEE ISCAS, pp. 1.407-1.410, 1994.
9. J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization," in IEEE TCAD, 10(3): 356-365, Mar. 1991.
10. M. Wang and M. Sarrafzadeh, "Congestion minimization during placement," in Proc. ACM ISPD, pp. 145-150, 1999.
11. W. Hou, X. Hong, W. Wu and Y. Cai, "A path-based timing-driven quadratic placement algorithm," in Proc. IEEE/ACM ASP-DAC, pp.745-748, 2003.
12. Y. Liu, X. Hong, Y. Cai, W. Wu, "CEP: A clock-driven ECO placement algorithm for standard-cell layout," in Proc. International Conference on ASIC, pp. 118-121, 2001.
13. N. Venkateswaran and D Bhatia, "Clock-skew constrained placement for row based designs," in Proc. IEEE ICCD, pp. 219-220, 1998.
14. B. Kernighan and S. Lin. "An Efficient Heuristic Procedure for Partitioning of Electrical Circuits". Bell System Technical Journal, pp. 291-307, 1970.
15. A. E. Dunlop and B. W. Kemighan, "A procedure for placement of standard-cell VLSI circuits," IEEE TCAD, vol. CAD-4, pp. 92-98, Jan. 1985.
16. N. Viswanathan and C.-N Chu, "FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model," in Proc. ACM ISPD, pp. 26-33, 2004.