PADE: A high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 756-761

  Ward, Samuel ^a   Ding, Duo ^a   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

datapath; extraction; physical design; placement

Indexed keywords

DATA PATHS; HIGH DIMENSIONAL DATA; LEARNING TECHNIQUES; NETLIST; PHYSICAL DESIGN; PLACEMENT; RANDOM LOGIC; SYMMETRICAL STRUCTURE; WIRE LENGTH;

COMPUTER AIDED DESIGN; EXTRACTION; WIRE;

CLUSTERING ALGORITHMS;

EID: 84863543772     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228497     Document Type: Conference Paper

References (22)

1. M.-C. Kim, D.-J. Lee, and I. L. Markov, "simPL: an effective placement algorithm," in Proc. ICCAD, pp. 649-656, 2010.
2. G.-J. Nam, C. J. Alpert, P. Villarrubia, B. Winter, and M. Yildiz., "ISPD 2005 placement contest benchmark suite," in Proc. ISPD, pp. 216-220, 2005.
3. G.-J. Nam and J. Cong, eds., Modern Circuit Placement: Best Practices and Results. New York, NY: Springer, 2007.
4. R. X. T. Nijssen and J. A. G. Jess, "Two-dimensional datapath regularity extraction," in IFIP Workshop on Logic and Architecture Synthesis, pp. 110-117, 1996.
5. S. I. Ward, D. A. Papa, Z. Li, C. N. Sze, C. J. Alpert, and E. Swartzlander, "Quantifying academic placer performance on custom designs," in Proc. ISPD, pp. 91-98, 2011.
6. S. I. Ward, M.-C. Kim, N. Viswanathan, Z. Li, C. Alpert, E. Swartzlander, and D. Z. Pan, "Keep it straight: Teaching placement how to better handle designs with datapaths," in Proc. ISPD, 2012.
7. N. Viswanathan, M. Pan, and C. Chu, "FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control," in Proceedings of ASPDAC, pp. 135-140, 2007.
8. A. Chowdhary, S. Kale, P. Saripella, N. Sehgal, and R. Gupta, "Extraction of functional regularity in datapath circuits," IEEE TCAD, vol. 18, no. 9, pp. 1279-1296, 1999.
9. A. Rosiello, F. Ferrandi, D. Pandini, and D. Sciuto, "A hash-based approach for functional regularity extraction during logic synthesis,"in Proc. ISVLSI, pp. 92-97, 2007.
10. S. Ono and P. H. Madden, "On structure and suboptimality in placement," in Proceedings of ASPDAC, pp. 331-336, 2005.
11. P. Ienne and A. GrieBing, "Practical experiences with standard-cell based datapath design tools," in Proceedings of DAC, pp. 396-401, 1998.
12. P. Spindler, U. Schlichtmann, and F. M. Johannes, "Kraftwerk2 - a fast force-directed quadratic placement approach using an accurate net model," IEEE TCAD, vol. 27, no. 8, pp. 1398-1411, 2008.
13. Q. Liu and M. Marek-Sadowska, "Pre-layout physical connectivity predictions with applications in clustering, placement and logic synthesis," in Proc. ICCAD, pp. 31-37, 2005.
14. T. Junttila and P. Kaski, "Engineering an efficient canonical labeling tool for large and sparse graphs," 2007.
15. R.-E. Fan, P.-H. Chen, and C.-J. Lin, "Working Set Selection Using Second Order Information for Training Support Vector Machines," in Journal of Machine Learning Research, 2005.
16. J. E. Beasley, ed., Advances in Linear and Integer Programming. New York, NY: Oxford University Press, Inc., 1996.
17. H. Shojaei, A. Davoodi, and J. Linderoth, "Congestion analysis for global routing via integer programming," in Proc. ICCAD, pp. 256-262, 2011.
18. G. Optimization, "The gurobi optimizer 4.5."http://www.gurobi. com/.
19. J. A. Roy, D. A. Papa, S. N. Adya, H. H. Chan, A. N. Ng, J. F. Lu, and I. L. Markov, "Capo: robust and scalable open-source min-cut floorplacer," in Proc. ISPD, pp. 224-226, 2005.
20. T. F. Chan, J. Cong, J. R. Shinnerl, K. Sze, and M. Xie, "mPL6: enhanced multilevel mixed-size placement," in Proc. ISPD, pp. 212-214, 2006.
21. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "A high-quality mixed-size analytical placer considering preplaced blocks and density constraints," in Proc. ICCAD, pp. 187-192, 2006.
22. T. Kutzschebauch and L. Stok, "Regularity driven logic synthesis," in Proc. ICCAD, pp. 439-446, 2000.