Hierarchical global floorplacement using simulated annealing and network flow area migration

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 1104-1105

  Choi, Wonjoon ^a   Bazargan, Kia ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA UTILIZATION; COMMUNICATION MECHANISMS; FLOOR-PLANNING; FLOORPLACEMENT; GLOBAL PLACEMENTS; INCREMENTAL CHANGES; NETWORK FLOW PROBLEMS; PLACEMENT METHODS;

EXHIBITIONS; SIMULATED ANNEALING; WIRE;

DESIGN;

EID: 84872317029     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253755     Document Type: Conference Paper

References (3)

1. S. N. Adya and I. L. Markov, Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement, International Symposium on Physical Design (ISPD), pp. 12-18, 2002
2. A. V. Goldberg, An Efficient Implementation of a Scaling Minimum-Cost Flow Algorithm, Journal of Algorithms, 22, pp. 1-29, 1997
3. G. Karypis and V. Kumar. Multilevel k-way Hyper-graph Partitioning. Design Automation Conference (DAC), pp. 343-348, 1999